公开(公告)号：US5098854A

公开(公告)日：1992-03-24

申请号：US609130

申请日：1990-11-01

申请人： Ashok K. Kapoor ,  Hemraj K. Hingarh

发明人： Ashok K. Kapoor ,  Hemraj K. Hingarh

IPC分类号： H01L21/331 ,  H01L21/60 ,  H01L21/768 ,  H01L29/423

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L29/42304 ,  H01L29/66272

摘要： A self-aligned silicide base contact structure for a bipolar transistor, and a process for fabricating the structure are disclosed. The structure has four key elements: a base region 36, a polycrystalline silicon emitter contact region 50, a spacer oxide 60 and 62, and a base contact 74 formed of metal silicide. The spacer oxide is an insulator that electrically isolates the side walls of the emitter contact region from the upper surface of the base region. The spacer oxide is a residual amount of oxide that is left on the side walls of the emitter contact region after anisotropic etching is used to remove most of a covering layer of oxide. The metal silicide base contact is created on an exposed upper surface of the base region, and is formed by first depositing a metal layer on the upper surface of the base region, and then heat treating. Where metal and silicon atoms are in contact, such as along the exposed upper surface of the base region, metal silicide forms.

摘要翻译： 公开了一种用于双极晶体管的自对准硅化物基极接触结构及其制造方法。 该结构具有四个关键元件：基极区域36，多晶硅发射极接触区域50，隔离氧化物60和62以及由金属硅化物形成的基极触点74。 间隔氧化物是将发射极接触区域的侧壁与基极区域的上表面电隔离的绝缘体。 间隔氧化物是在使用各向异性蚀刻去除大部分氧化物覆盖层之后残留在发射极接触区域的侧壁上的氧化物的残留量。 金属硅化物基极接触在基部区域的暴露的上表面上产生，并且通过首先在基底区域的上表面上沉积金属层，然后进行热处理而形成。 当金属和硅原子接触时，例如沿着暴露的基区的上表面，形成金属硅化物。

公开(公告)号：US4298402A

公开(公告)日：1981-11-03

申请号：US118291

申请日：1980-02-04

申请人： Hemraj K. Hingarh

发明人： Hemraj K. Hingarh

IPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L21/32155 ,  H01L21/033 ,  H01L21/8222 ,  H01L29/735

摘要： A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

摘要翻译： 当为发射极和基极区域注入离子时，通过使用掺杂多晶硅层作为离子注入掩模来制造具有窄宽度基底的表面取向横向双极晶体管。 在形成掺杂多晶硅掩模时，在半导体衬底的表面上形成第一掺杂剂掩模材料层，在第一层上形成第二层未掺杂的多晶硅，在第二层上形成第三层掺杂剂掩模材料 层。 去除第二层和第三层的部分，并且掺杂剂扩散到第二层的暴露边缘部分中。 然后去除第三层和第二层的未掺杂部分，从而仅在第一层上仅留下第二层的掺杂部分。

公开(公告)号：US4084174A

公开(公告)日：1978-04-11

申请号：US657439

申请日：1976-02-12

申请人： Richard E. Crippen ,  Hemraj K. Hingarh ,  Peter W. J. Verhofstadt

发明人： Richard E. Crippen ,  Hemraj K. Hingarh ,  Peter W. J. Verhofstadt

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L29/48 ,  H01L29/72

CPC分类号： H01L27/0233

摘要： A graduated multiple collector structure for inverted vertical bipolar transistors, integrated injection logic devices and the like. The invention increases the gain of more distant collectors toward which current flows laterally past intervening collectors from a base contact, and injector or the like. The series resistance drop and the current loss in the base-emitter junction are compensated for by progressively increasing the effective area of collectors further distant from the source of the base current. Although the graduated collector structure is applicable to a wide variety of semiconductor devices, it is particularly well suited for use in oxide-isolated integrated injection logic gates. A mathematical model is provided which can help to optimize designs incorporating the graduated collector structure.

公开(公告)号：US5563801A

公开(公告)日：1996-10-08

申请号：US132558

申请日：1993-10-06

申请人： Ven L. Lee ,  Hemraj K. Hingarh

发明人： Ven L. Lee ,  Hemraj K. Hingarh

IPC分类号： G06F17/50 ,  H01L27/118

CPC分类号： H01L27/11807 ,  G06F17/5068

摘要： A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.

摘要翻译： 教授了独特的门阵列单元和ASIC库开发方法，其不需要新的模拟或新的位置和路由将给定的设备设计端口连接到来自不同供应商的同一代工艺技术。 该方法利用来自不同供应商的最小设计规则，而无需重新路由物理数据库。 该方法在多个替代源上均衡宏单元库的功能和时序特征。

公开(公告)号：US4628339A

公开(公告)日：1986-12-09

申请号：US794586

申请日：1985-11-04

申请人： Madhukar B. Vora ,  Hemraj K. Hingarh

发明人： Madhukar B. Vora ,  Hemraj K. Hingarh

IPC分类号： H01L21/84 ,  H01L23/528 ,  H01L27/102 ,  H01L29/04 ,  H01L29/872 ,  H01L29/48 ,  H01L27/10 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L23/5283 ,  H01L27/1021 ,  H01L29/04 ,  H01L29/872 ,  H01L2924/0002 ,  Y10S257/926

摘要： A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

摘要翻译： 公开了适用于在相互垂直的铝条和金属硅化物条之间的期望位置处形成大阵列的肖特基二极管的工艺和结构。 本发明在创建只读存储器和可编程逻辑阵列中特别有用，并且允许比先前的结构更紧凑地制造肖特基二极管。

公开(公告)号：US4106090A

公开(公告)日：1978-08-08

申请号：US760063

申请日：1977-01-17

申请人： Charles R. Erickson ,  Hemraj K. Hingarh ,  Robert Moeckel ,  Dan Wilnai

发明人： Charles R. Erickson ,  Hemraj K. Hingarh ,  Robert Moeckel ,  Dan Wilnai

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F7/48

CPC分类号： G06F15/7864

摘要： A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor.The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory.An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU. Bidirectional three-state logic is used to enable both input and output data, as well as memory addresses, to be transmitted over the same bus thereby simplifying design. In addition, provision is made for coupling an operator console into a system formed around the processor of this invention, thus allowing for a user to interface with the system.

摘要翻译： 中央处理单元（CPU）与外部存储器和输入/输出设备结合使用以形成微计算机系统。 CPU是一个16位固定字长处理器，单片集成到单个半导体芯片上，采用二进制补码运算进行计算。 CPU包括算术逻辑单元（ALU），累加器，数据路径多路复用器，程序计数器装置和可编程逻辑阵列，以控制处理器的操作。

公开(公告)号：US06240008B1

公开(公告)日：2001-05-29

申请号：US09590443

申请日：2000-06-09

申请人： Subramani Kengeri ,  Hemraj K. Hingarh

发明人： Subramani Kengeri ,  Hemraj K. Hingarh

IPC分类号： G11C1124

CPC分类号： G11C11/4096 ,  G11C11/4091

摘要： A dynamic random access memory (DRAM) having a conventional cell layout and having its data access path adapted to access a ‘zero’ faster than a ‘one.’ The DRAM comprising two capacitors coupled respectively to two neighboring word lines. The two capacitors are also coupled respectively to two neighboring bit lines via two pass gates. Data is represented as complementary data bits on the two capacitors. In so doing, a ‘zero’ is ensured to be stored in either one of the two capacitors. A voltage level ‘zero’ is in turn ensured to be maintained on the bit line coupled to the capacitor that stores the ‘zero’ data bit. The sense amplifier and the write driver take advantage of the fact that a voltage level ‘zero’ is ensured to be maintained in either one of the two bit lines. Each of a sense amplifier and a write driver, as parts of the DRAM's data access path, amplifies a ‘zero’ and a ‘one’ unequally by amplifying the ‘zero’ faster than the ‘one.’ Access time is thus improved. The DRAM does not need to operate in the differential sensing mode. The DRAM can operate in either the differential sensing mode or the conventional mode. The switch between the differential and the conventional sensing modes can be implemented without having to alter the cell layout of a conventional DRAM.

摘要翻译： 动态随机存取存储器（DRAM）具有传统的单元布局并且具有适于比“一”更快地访问“零”的数据访问路径。 DRAM包括分别耦合到两个相邻字线的两个电容器。 两个电容器也通过两个通路分别耦合到两个相邻的位线。 数据被表示为两个电容器上的互补数据位。 在这样做时，确保将“零”存储在两个电容器中的任何一个中，然后确保电压电平“零”保持在耦合到存储“零”数据位的电容器的位线上 读出放大器和写入驱动器利用了两个位线之一中保持电压电平“零”的事实。 作为DRAM的数据存取路径的一部分的读出放大器和写入驱动器，通过比“1”更快的放大“零”，不平等地放大“零”和“1”。 从而改善了访问时间。 DRAM不需要在差分感测模式下工作。 DRAM可以在差分感测模式或常规模式中操作。 可以实现差分和传统感测模式之间的切换，而不必改变常规DRAM的单元布局。

公开(公告)号：US4908679A

公开(公告)日：1990-03-13

申请号：US570408

申请日：1984-01-12

申请人： Madhukar B. Vora ,  Hemraj K. Hingarh

发明人： Madhukar B. Vora ,  Hemraj K. Hingarh

IPC分类号： H01L21/329 ,  H01L21/70 ,  H01L21/84 ,  H01L29/04 ,  H01L29/872

CPC分类号： H01L29/66143 ,  H01L21/70 ,  H01L21/84 ,  H01L29/04 ,  H01L29/872

摘要： A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.

摘要翻译： 根据以下步骤制造肖特基二极管：在下面的介电层上形成金属硅化物层，在金属硅化物层的上表面上形成多晶硅层，在第二电介质层的上表面上形成第二电介质层 多晶硅层和图案化第二电介质层以形成通过第二电介质层的接触窗到多晶硅层的暴露表面区域，以及形成与暴露表面区域的金属接触。

公开(公告)号：US4583168A

公开(公告)日：1986-04-15

申请号：US530996

申请日：1983-09-12

申请人： Richard Pang ,  Hemraj K. Hingarh

发明人： Richard Pang ,  Hemraj K. Hingarh

IPC分类号： G06F15/78 ,  G06F12/00

CPC分类号： G06F15/7832

摘要： A microprocessor integrated circuit (50) has a read only memory (ROM) (400) which is X and Y addressible and is word, bit and page oriented. The microprocessor integrated circuit (50) has a main injector bus (602) and a ground return bus (604) with a branch ground bus (608) connected to the ground return bus (604) through a ground-balancing resistor (610) in a data path. The circuit (50) has a register file (82) with registers (622) connected to a local bus (604). The local busses (604) are connected to a main bus (602) through a multiplexer (605). The microprocessor integrated circuit (50) includes a D-type flip-flop circuit (700) with asynchronous clear and preset. A latch dual port random access memory (RAM) circuit (900) is employed in the register file (82) of the microprocessor integrated circuit (50).

摘要翻译： 微处理器集成电路（50）具有只读存储器（ROM）（400），其是X和Y可寻址的，并且是字，位和页面定向的。 微处理器集成电路（50）具有主注射器总线（602）和接地返回总线（604），其中分支接地总线（608）通过接地平衡电阻（610）连接到接地返回总线（604） 数据路径。 电路（50）具有寄存器文件（82），其寄存器（622）连接到本地总线（604）。 本地总线（604）通过多路复用器（605）连接到主总线（602）。 微处理器集成电路（50）包括具有异步清除和预设的D型触发器电路（700）。 在微处理器集成电路（50）的寄存器文件（82）中采用锁存双端口随机存取存储器（RAM）电路（900）。

公开(公告)号：US4115797A

公开(公告)日：1978-09-19

申请号：US729045

申请日：1976-10-04

申请人： Hemraj K. Hingarh ,  Richard E. Crippen

发明人： Hemraj K. Hingarh ,  Richard E. Crippen

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L29/10 ,  H01L21/22 ,  H01L21/82 ,  H01L27/04

CPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L27/0233 ,  H01L29/1004 ,  Y10S148/087

摘要： An integrated injection logic semiconductor structure having a double diffused lateral PNP transistor and an inverted vertical NPN transistor includes an extended region of epitaxial silicon doped N type by introduction of suitable impurity from two separate regions of the semiconductor surface. This extended N type region, which functions as the base of the PNP transistor, allows an adjoining P type region, which in prior art structures served only as the collector, to be utilized as both the collector and the collector contact, thereby reducing the size of the semiconductor structure. Said N type region substantially lessens the series resistance between the base of the NPN transistor and the collector of the PNP transistor, to thereby facilitate manufacture of integrated injection logic circuits operating faster, at higher current levels, and at higher gain than integrated injection logic circuits not utilizing this invention. The extended N type region also facilitates the manufacture of faster multiple collector integrated circuit structures. Additionally, this invention will be useful in fabricating a more compact double diffused lateral transistor structure.

摘要翻译： 具有双扩散横向PNP晶体管和反向垂直NPN晶体管的集成注入逻辑半导体结构通过从半导体表面的两个独立区域引入合适的杂质而包括外延硅掺杂N型扩展区域。 作为PNP晶体管的基极的这种扩展型N型区域允许在现有技术中仅用作集电极的相邻的P型区域用作集电极和集电极接触两者，从而减小尺寸 的半导体结构。 所述N型区域基本上减轻了NPN晶体管的基极和PNP晶体管的集电极之间的串联电阻，从而有助于在更高的电流水平下以较高的集成注入逻辑电路和更高的增益运行的集成注入逻辑电路的制造 不利用本发明。 扩展N型区域也有助于制造更快的多集电极集成电路结构。 另外，本发明将有助于制造更紧凑的双扩散横向晶体管结构。