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公开(公告)号：US20220116002A1
公开(公告)日：2022-04-14
申请号：US17491578
申请日：2021-10-01
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
IPC: H03F3/45
Abstract: A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.
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公开(公告)号：US12136878B2
公开(公告)日：2024-11-05
申请号：US17933877
申请日：2022-09-21
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A multi-stage amplifier circuit includes: a front stage amplification circuit, for generating a front stage amplification signal according to a difference between a primary reference signal and a primary feedback signal; an output adjustment circuit, for generating a driving signal according to the front stage amplification signal; and an output transistor, controlled by the driving signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by a differential current of the front stage amplification signal; and an impedance adjustment device biased by the differential current. A resistance of the impedance adjustment device is determined by a difference between an adjustment feedback signal and an adjustment reference signal. The driving signal is determined by a product of a resistance of the impedance adjustment device multiplied by the differential current of the front stage amplification signal, and a drain-source voltage of the adjustment transistor.
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公开(公告)号：US20220190788A1
公开(公告)日：2022-06-16
申请号：US17552310
申请日：2021-12-15
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A parallel input and dynamic cascaded OTA (operational transconductance amplifier includes: plural sub-OTAs which generate corresponding plural transconductance output currents according to corresponding plural differential input voltages; and at least one cascading capacitor which is cascaded between a first sub-OTA and a second sub-OTA. A second transconductance output current generated by the second sub-OTA is coupled through the cascading capacitor to generate a transient bias current on a common mode bias node of the first sub-OTA, thus providing the transient bias current to a differential pair circuit of the first sub-OTA in a case when a transient variation occurs in the differential input voltage corresponding to the first sub-OTA, so that a loop bandwidth and a response speed during a transient state are enhanced.
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公开(公告)号：US20210191439A1
公开(公告)日：2021-06-24
申请号：US17033810
申请日：2020-09-27
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A linear regulator circuit having fast transient response includes an error amplifier (EA) circuit and an output stage circuit. The EA circuit amplifies a difference between a feedback signal and a reference signal to generate an error amplified signal. The output stage circuit includes at least one output power switch which is controlled by the error amplified signal to generate an output signal at an output node. The EA circuit includes at least one pre-stage amplifier circuit which includes a current source circuit, a differential input circuit, a first, a second and a third current mirror circuits and at least one feedback capacitor. One differential transistor of the differential input circuit, the first and the second current mirror circuit form a positive potential feedback (PPFB) loop. The feedback capacitor is coupled between the output node and at least one inverting node at the PPFB loop.
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公开(公告)号：US20230216401A1
公开(公告)日：2023-07-06
申请号：US17933877
申请日：2022-09-21
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A multi-stage amplifier circuit includes: a front stage amplification circuit, for generating a front stage amplification signal according to a difference between a primary reference signal and a primary feedback signal; an output adjustment circuit, for generating a driving signal according to the front stage amplification signal; and an output transistor, controlled by the driving signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by a differential current of the front stage amplification signal; and an impedance adjustment device biased by the differential current. A resistance of the impedance adjustment device is determined by a difference between an adjustment feedback signal and an adjustment reference signal. The driving signal is determined by a product of a resistance of the impedance adjustment device multiplied by the differential current of the front stage amplification signal, and a drain-source voltage of the adjustment transistor.
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Patent Agency Ranking
公开(公告)号：US11496105B2
公开(公告)日：2022-11-08
申请号：US17491578
申请日：2021-10-01
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
IPC: H03F3/45
Abstract: A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.
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7.发明申请公开(公告)号：US20210028747A1
公开(公告)日：2021-01-28
申请号：US16923786
申请日：2020-07-08
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.
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公开(公告)号：US11340643B2
公开(公告)日：2022-05-24
申请号：US17033810
申请日：2020-09-27
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A linear regulator circuit having fast transient response includes an error amplifier (EA) circuit and an output stage circuit. The EA circuit amplifies a difference between a feedback signal and a reference signal to generate an error amplified signal. The output stage circuit includes at least one output power switch which is controlled by the error amplified signal to generate an output signal at an output node. The EA circuit includes at least one pre-stage amplifier circuit which includes a current source circuit, a differential input circuit, a first, a second and a third current mirror circuits and at least one feedback capacitor. One differential transistor of the differential input circuit, the first and the second current mirror circuit form a positive potential feedback (PPFB) loop. The feedback capacitor is coupled between the output node and at least one inverting node at the PPFB loop.
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9.发明授权公开(公告)号：US11146217B2
公开(公告)日：2021-10-12
申请号：US16923786
申请日：2020-07-08
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.
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公开(公告)号：US12143070B2
公开(公告)日：2024-11-12
申请号：US17552310
申请日：2021-12-15
Applicant: Richtek Technology Corporation
Inventor： Min-Hung Hu
Abstract: A parallel input and dynamic cascaded OTA (operational transconductance amplifier includes: plural sub-OTAs which generate corresponding plural transconductance output currents according to corresponding plural differential input voltages; and at least one cascading capacitor which is cascaded between a first sub-OTA and a second sub-OTA. A second transconductance output current generated by the second sub-OTA is coupled through the cascading capacitor to generate a transient bias current on a common mode bias node of the first sub-OTA, thus providing the transient bias current to a differential pair circuit of the first sub-OTA in a case when a transient variation occurs in the differential input voltage corresponding to the first sub-OTA, so that a loop bandwidth and a response speed during a transient state are enhanced.
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