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公开(公告)号:US20230198473A1
公开(公告)日:2023-06-22
申请号:US18056329
申请日:2022-11-17
Applicant: Richtek Technology Corporation
Inventor: Chun-Jen Yu , Ssu-Wei Huang , Hsuan-Kai Wang , Chi-Jen Yang , Hsien-Chih She
CPC classification number: H03F1/14 , H03F1/42 , H03F2200/222
Abstract: An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.