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公开(公告)号：US10114750B2
公开(公告)日：2018-10-30
申请号：US13451010
申请日：2012-04-19
IPC分类号： G06F3/06 , G06F12/0855 , G06F12/0882
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
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公开(公告)号：US08612690B2
公开(公告)日：2013-12-17
申请号：US13426647
申请日：2012-03-22
CPC分类号： G06F12/1054 , G06F12/0864 , G06F12/1045 , G06F12/1063 , Y02D10/13
摘要： Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
摘要翻译： 公开了数据高速缓存的实施例，其提供了对数据高速缓存的物理标记的标签阵列的访问的数量的大量减少。 通常，数据高速缓存包括存储数据元素，物理标记的标签阵列和虚拟标记的标签阵列的数据阵列。 在一个实施例中，虚拟标记的标签阵列接收虚拟地址。 如果虚拟标记的标签阵列中的虚拟地址匹配，则虚拟标记的标签阵列将数据阵列中的虚拟地址标记在虚拟标记的数组中。 此外，在一个实施例中，虚拟标记的标签阵列禁用物理标记的标签阵列。 使用由虚拟标记的标签数组输出的方式，寻址数据数组中所需的数据元素。
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3.发明申请PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE DATA FILL BUFFERS 审中-公开防止参考数据填充缓冲区的高速局部性的偏移公开(公告)号：US20130191559A1
公开(公告)日：2013-07-25
申请号：US13451010
申请日：2012-04-19
IPC分类号： G06F3/00
CPC分类号： G06F12/0859 , G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
摘要翻译： 本公开涉及以高参考时间局部性访问存储器内容。 本公开的实施例将内容存储在数据缓冲器中，确定数据缓冲器的内容具有高的参考时间局部性，并且针对针对内容的每个操作而不是存储内容的高速缓存来访问数据缓冲器。
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4.发明授权Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods 有权确定虚拟标记缓存中的别名地址的缓存命中/未命中，以及相关的系统和方法公开(公告)号：US09110830B2
公开(公告)日：2015-08-18
申请号：US13478149
申请日：2012-05-23
CPC分类号： G06F12/1063 , G06F12/1045
摘要： Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually-tagged cache(s) are disclosed. In one embodiment, virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses, respectively. The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner, the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses, even in the presence of aliased addressing.
摘要翻译： 公开了用于确定虚拟标记的高速缓存中的混叠地址的高速缓存命中/未命中的装置和相关系统和方法。 在一个实施例中，提供了用于VIVT高速缓存的虚拟混叠高速缓存命中/未命中检测器。 检测器包括TLB，其被配置为基于第一虚拟地址从VIVT高速缓存中接收第一虚拟地址和第二虚拟地址，该第一虚拟地址和第二虚拟地址是从索引读取到VIVT高速缓存中产生的。 TLB还被配置为分别生成从第一和第二虚拟地址转换的第一和第二物理地址。 检测器还包括比较器，其被配置为基于第一和第二物理地址的比较来接收第一物理地址和第二物理地址并且实现别名高速缓存命中/未命中指示符的生成。 以这种方式，即使在存在别名寻址的情况下，虚拟混叠高速缓存命中/未命中检测器也能正确地产生高速缓存命中和高速缓存未命中。
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5.发明申请Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged Cache(s), and Related Systems and Methods 有权确定几何标记缓存中的别名地址的缓存命中/错误，以及相关系统和方法公开(公告)号：US20130185520A1
公开(公告)日：2013-07-18
申请号：US13478149
申请日：2012-05-23
IPC分类号： G06F12/08
CPC分类号： G06F12/1063 , G06F12/1045
摘要： Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually-tagged cache(s) are disclosed. In one embodiment, virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses, respectively, The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner, the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses, even in the presence of aliased addressing.
摘要翻译： 公开了用于确定虚拟标记的高速缓存中的混叠地址的高速缓存命中/未命中的装置和相关系统和方法。 在一个实施例中，提供了用于VIVT高速缓存的虚拟混叠高速缓存命中/未命中检测器。 检测器包括TLB，其被配置为基于第一虚拟地址从VIVT高速缓存中接收第一虚拟地址和第二虚拟地址，该第一虚拟地址和第二虚拟地址是从索引读取到VIVT高速缓存中产生的。 所述TLB还被配置为分别从所述第一和第二虚拟地址生成第一和第二物理地址。所述检测器还包括比较器，被配置为接收所述第一和第二物理地址并且实现混叠高速缓存命中/未命中指示符的生成 基于第一和第二物理地址的比较。 以这种方式，即使在存在别名寻址的情况下，虚拟混叠高速缓存命中/未命中检测器也能正确地产生高速缓存命中和高速缓存未命中。
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公开(公告)号：US20130185473A1
公开(公告)日：2013-07-18
申请号：US13426647
申请日：2012-03-22
CPC分类号： G06F12/1054 , G06F12/0864 , G06F12/1045 , G06F12/1063 , Y02D10/13
摘要： Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
摘要翻译： 公开了数据高速缓存的实施例，其提供了对数据高速缓存的物理标记的标签阵列的访问的数量的大量减少。 通常，数据高速缓存包括存储数据元素，物理标记的标签阵列和虚拟标记的标签阵列的数据阵列。 在一个实施例中，虚拟标记的标签阵列接收虚拟地址。 如果虚拟标记的标签阵列中的虚拟地址匹配，则虚拟标记的标签阵列将数据阵列中的虚拟地址标记在虚拟标记的数组中。 此外，在一个实施例中，虚拟标记的标签阵列禁用物理标记的标签阵列。 使用由虚拟标记的标签数组输出的方式，寻址数据数组中所需的数据元素。
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公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译： 本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。 处理系统包括多个存储器件和多个处理器。 每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。 处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。
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8.发明授权公开(公告)号：US08078803B2
公开(公告)日：2011-12-13
申请号：US11669245
申请日：2007-01-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译： 技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。
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9.发明授权Method and apparatus for segregating shared and non-shared data in cache memory banks 有权用于在高速缓存存储体中隔离共享和非共享数据的方法和装置公开(公告)号：US07353319B2
公开(公告)日：2008-04-01
申请号：US11144207
申请日：2005-06-02
IPC分类号： G06F12/06
CPC分类号： G06F12/0848 , G06F12/0831 , G06F12/0837 , Y02D10/13
摘要： In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated for holding non-shared data. A non-shared data bank may be designated exclusively for holding non-shared data, so that shared data accesses do not interfere with non-shared accesses to that bank. Also, a shared data bank may be designated exclusively for holding shared data, and one or more banks may be designated for holding both shared and non-shared data. An access control circuit directs shared and non-shared accesses to respective banks based on receiving a shared indication signal in association with the accesses. Further, in one or more embodiments, the access control circuit reconfigures one or more bank designations responsive to a bank configuration signal.
摘要翻译： 在多处理器系统中，控制对给定处理器的存储高速缓存的访问，使得共享数据访问被定向到指定用于保存共享数据的一个或多个库和/或非共享数据访问被定向到指定用于保存非共享数据的一个或多个库 共享数据。 非共享数据库可以专门用于保存非共享数据，使得共享数据访问不会干扰对该银行的非共享访问。 此外，共享数据库可以被专门用于保存共享数据，并且可以指定一个或多个存储体来保存共享和非共享数据。 访问控制电路基于接收与访问相关联的共享指示信号，将共享和非共享访问指向各个存储体。 此外，在一个或多个实施例中，访问控制电路响应于存储体配置信号重新配置一个或多个存储体指定。
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10.发明申请Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions 有权在多个内存区域自动排序强顺序，设备和独占交易公开(公告)号：US20130151799A1
公开(公告)日：2013-06-13
申请号：US13315370
申请日：2011-12-09
申请人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
发明人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
IPC分类号： G06F12/00
CPC分类号： G06F13/1621
摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。
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