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    Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering
    2.
    发明申请
    Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering 有权
    使用基本块矢量聚类和飞行矢量聚类的集成电路设计模型性能评估的方法和装置

    公开(公告)号：US20090276191A1

    公开(公告)日：2009-11-05

    申请号：US12112035

    申请日：2008-04-30

    申请人： Robert H. Bell, JR. ,  Wen-Tzer Thomas Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell, JR. ,  Wen-Tzer Thomas Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G01R31/318357 ,  G06F11/3428 ,  G06F11/3457 ,  G06F11/3664

    摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。 增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。 增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。 增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。 增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。 设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

    Scaling instruction intervals to identify collection points for representative instruction traces
    3.
    发明授权
    Scaling instruction intervals to identify collection points for representative instruction traces 失效
    缩放指令间隔以标识代表性指令轨迹的收集点

    公开(公告)号：US08091073B2

    公开(公告)日：2012-01-03

    申请号：US11758031

    申请日：2007-06-05

    申请人： Robert H. Bell, Jr. ,  Wen-Tzer T. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell, Jr. ,  Wen-Tzer T. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F9/44

    CPC分类号： G06F11/36

    摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.

    摘要翻译： 提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。 针对一组阶段中的每个阶段计算相位指令预算。 相位指令预算基于与每个阶段相关联的权重和全局指令预算。 为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。 确定区间指标集内的指令是否符合全球指令预算。 响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

    Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces
    4.
    发明申请
    Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
    缩放指令间隔以识别代表性指令跟踪的收集点

    公开(公告)号：US20080307203A1

    公开(公告)日：2008-12-11

    申请号：US11758031

    申请日：2007-06-05

    申请人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell, JR. ,  Wen-Tzer T. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F9/30

    CPC分类号： G06F11/36

    摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.

    摘要翻译： 提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。 针对一组阶段中的每个阶段计算相位指令预算。 相位指令预算基于与每个阶段相关联的权重和全局指令预算。 为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。 确定区间指标集内的指令是否符合全球指令预算。 响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

    Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information
    5.
    发明授权
    Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information 有权
    使用包括数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置

    公开(公告)号：US07844928B2

    公开(公告)日：2010-11-30

    申请号：US11972747

    申请日：2008-01-11

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。 基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。 基准软件从应用软件的指令轨迹生成基本块向量BBV。 基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。 基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。 基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。 设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

    Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information
    6.
    发明申请
    Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information 有权
    使用基本块向量和包含微体系结构信息的飞越向量评估集成电路设计模型性能的方法和装置

    公开(公告)号：US20090199138A1

    公开(公告)日：2009-08-06

    申请号：US12026141

    申请日：2008-02-05

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F11/3457 ,  G06F11/3428

    摘要： A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的IC测试应用采样软件程序。 测试应用采样软件包括跟踪，仿真点，CPI错误，聚类等程序。 IC设计人员利用测试应用程序采样软件，通过测试软件应用来评估IC设计的性能特征。 测试应用采样软件从测试应用软件的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。 测试应用程序采样软件分析其用于生成FBV的微体系结构依赖信息。 测试应用采样软件使用指令预算方法从BBV和FBV数据生成降低的代表性测试应用软件程序。 设计人员使用带有测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

    Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information
    7.
    发明授权
    Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information 有权
    使用基本块向量和飞越向量包括微架构依赖信息来评估集成电路设计模型性能的方法和装置

    公开(公告)号：US07770140B2

    公开(公告)日：2010-08-03

    申请号：US12026141

    申请日：2008-02-05

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F11/3457 ,  G06F11/3428

    摘要： A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的IC测试应用采样软件程序。 测试应用采样软件包括跟踪，仿真点，CPI错误，聚类等程序。 IC设计人员利用测试应用程序采样软件，通过测试软件应用来评估IC设计的性能特征。 测试应用采样软件从测试应用软件的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。 测试应用程序采样软件分析其用于生成FBV的微体系结构依赖信息。 测试应用采样软件使用指令预算方法从BBV和FBV数据生成降低的代表性测试应用软件程序。 设计人员使用带有测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

    Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors that Include Data Dependent Information
    8.
    发明申请
    Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors that Include Data Dependent Information 有权
    使用包含数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置

    公开(公告)号：US20090183127A1

    公开(公告)日：2009-07-16

    申请号：US11972747

    申请日：2008-01-11

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。 基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。 基准软件从应用软件的指令轨迹生成基本块向量BBV。 基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。 基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。 基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。 设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

    IDENTIFYING LOAD-HIT-STORE CONFLICTS
    9.
    发明申请
    IDENTIFYING LOAD-HIT-STORE CONFLICTS 有权

    公开(公告)号：US20140075158A1

    公开(公告)日：2014-03-13

    申请号：US13611006

    申请日：2012-09-12

    申请人： Venkat R. Indukuru ,  Alexander E. Mericas ,  Satish K. Sadasivam ,  Madhavi G. Valluri

    发明人： Venkat R. Indukuru ,  Alexander E. Mericas ,  Satish K. Sadasivam ,  Madhavi G. Valluri

    IPC分类号： G06F9/312

    CPC分类号： G06F9/44552 ,  G06F9/3834

    摘要： A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

    Identifying load-hit-store conflicts
    10.
    发明授权
    Identifying load-hit-store conflicts 有权
    识别加载命中商店冲突

    公开(公告)号：US09229745B2

    公开(公告)日：2016-01-05

    申请号：US13611006

    申请日：2012-09-12

    申请人： Venkat R. Indukuru ,  Alexander E. Mericas ,  Satish K. Sadasivam ,  Madhavi G. Valluri

    发明人： Venkat R. Indukuru ,  Alexander E. Mericas ,  Satish K. Sadasivam ,  Madhavi G. Valluri

    IPC分类号： G06F9/00 ,  G06F9/445 ,  G06F9/38

    CPC分类号： G06F9/44552 ,  G06F9/3834

    摘要： A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

    摘要翻译： 计算设备识别导致加载命中 - 存储冲突的加载指令和存储指令对。 处理器标记指示处理器从存储器加载第一数据集的第一加载指令。 处理器将特定目的寄存器中的第一加载指令所在的地址存储在存储器中。 处理器确定第一个加载指令与第一个存储指令的加载命中 - 存储冲突的位置。 如果处理器确定第一加载指令具有与第一存储指令的加载命中存储冲突，则处理器将第一数据集所在的地址存储在第二专用寄存器中的存储器中，对存储的第一数据集进行标记 通过第一存储指令，将第一存储指令所在的地址存储在第三专用寄存器中，并增加冲突计数器。