公开(公告)号：US07818694B2

公开(公告)日：2010-10-19

申请号：US12342353

申请日：2008-12-23

申请人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

发明人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。