公开(公告)号：US07818694B2

公开(公告)日：2010-10-19

申请号：US12342353

申请日：2008-12-23

Applicant: Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

Inventor： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Abstract translation: 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

公开(公告)号：US20070245283A1

公开(公告)日：2007-10-18

申请号：US11279758

申请日：2006-04-14

Applicant: Robert Allen ,  Michael Gray ,  Fuok-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker

Inventor： Robert Allen ,  Michael Gray ,  Fuok-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.

Abstract translation: 一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。 该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置 使用线性规划解决方案的结果的至少一个小区。

公开(公告)号：US20070143728A1

公开(公告)日：2007-06-21

申请号：US11676185

申请日：2007-02-16

Applicant: John Cohn ,  Jason Hibbeler ,  Anthony Stamper ,  Jed Rankin

Inventor： John Cohn ,  Jason Hibbeler ,  Anthony Stamper ,  Jed Rankin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

Abstract translation: 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。

公开(公告)号：US20070136714A1

公开(公告)日：2007-06-14

申请号：US11275076

申请日：2005-12-08

Applicant: John Cohn ,  Jason Hibbeler ,  Gustavo Tellez

Inventor： John Cohn ,  Jason Hibbeler ,  Gustavo Tellez

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Embodiments herein present a method, service, computer program product, etc. or performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

Abstract translation: 本文的实施例提供了一种方法，服务，计算机程序产品等，或为设计执行屈服感知IC路由。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。

公开(公告)号：US20070099236A1

公开(公告)日：2007-05-03

申请号：US11163696

申请日：2005-10-27

Applicant: Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl

Inventor： Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl

IPC: C40B30/02

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

Abstract translation: 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

公开(公告)号：US20060265684A1

公开(公告)日：2006-11-23

申请号：US10908593

申请日：2005-05-18

Applicant: Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

Inventor： Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

Abstract translation: 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用交替 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

公开(公告)号：US20060101356A1

公开(公告)日：2006-05-11

申请号：US10904225

申请日：2004-10-29

Applicant: Robert Allen ,  Cam Endicott ,  Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker ,  Xin Yuan

Inventor： Robert Allen ,  Cam Endicott ,  Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker ,  Xin Yuan

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.

Abstract translation: 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

公开(公告)号：US20050050500A1

公开(公告)日：2005-03-03

申请号：US10604962

申请日：2003-08-28

Applicant: Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

Inventor： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5068

Abstract: The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US07503020B2

公开(公告)日：2009-03-10

申请号：US11424922

申请日：2006-06-19

Applicant: Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

Inventor： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Abstract translation: 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。