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公开(公告)号：US20080222583A1
公开(公告)日：2008-09-11
申请号：US11930820
申请日：2007-10-31
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译： 核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常，标准化模型提供比所需更多的功能。 可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。 因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。
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公开(公告)号：US06865502B2
公开(公告)日：2005-03-08
申请号：US09826035
申请日：2001-04-04
IPC分类号： G01R31/319 , G01R31/14 , G06F19/00
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
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公开(公告)号：US07729877B2
公开(公告)日：2010-06-01
申请号：US11930820
申请日：2007-10-31
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译： 核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常，标准化模型提供比所需更多的功能。 可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。 因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。
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公开(公告)号：US07353131B2
公开(公告)日：2008-04-01
申请号：US10986773
申请日：2004-11-15
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译： 核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常，标准化模型提供比所需更多的功能。 可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。 因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。
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5.发明授权Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs 失效开发可重用软件的方法，用于片上系统集成电路设计的有效验证公开(公告)号：US06539522B1
公开(公告)日：2003-03-25
申请号：US09494907
申请日：2000-01-31
申请人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.
摘要翻译： 一种用于开发用于片上系统（SOC）集成电路设计的有效验证的可重用软件的方法。 验证软件用于生成和应用测试用例，以刺激模拟中SOC设计（“核心”）的组件; 观察结果并用于对设计进行设计。 该软件是分级的，实现生成测试用例的上级测试应用程序代码和验证结果之间的分区，以及与正在模拟的内核接口的低级设备驱动程序代码，以应用由上级代码生成的测试用例 在硬件层面的操作。 测试应用程序和支持低级设备驱动程序对被使用并重新用于在SOC开发过程中测试其相应的组件核心，通过创建更高级别的测试控制程序来控制已经开发的测试应用程序和设备驱动程序的选定组合 测试SOC组件组合的程序。 该方法提供SOC设计的有效验证，从而缩短了SOC产品的上市时间，因为随着验证软件的开发和存储，可以通过创建相对较少的高可用性测试来测试日益复杂的核心组合， 重新使用已经存在的低级软件的级别测试程序。 最终，可以简化验证复杂SOC设计的任务，以开发单个芯片特定的测试程序，该测试程序从已经存在的测试应用程序，设备驱动程序和测试控制程序中进行选择，以执行芯片特定的内核组合的现实测试 。
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6.发明授权Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor 失效有效验证包括嵌入式处理器在内的片上系统集成电路设计的方法公开(公告)号：US06427224B1
公开(公告)日：2002-07-30
申请号：US09494564
申请日：2000-01-31
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator. Because most of the verification software executes externally to the simulator while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions is removed from the simulator. As a result, faster verification is enabled.
摘要翻译： 一种使用验证软件来测试包括嵌入式处理器在内的片上系统（SOC）设计的方法。 验证软件用于生成和应用测试用例，以刺激模拟中的SOC设计; 观察结果并用于对设计进行设计。 包括嵌入式处理器的SOC设计的验证通常非常慢。 为了在这种情况下提供加速验证模式，在本发明的方法中，验证软件被分为更高级别的控制代码和较低级别的设备驱动程序代码。 上级代码执行决策，测试初始化，测试随机化，多任务处理以及测试结果与预期结果的比较等功能。 低级代码接口与核心正在被模拟，以便在硬件级别的操作上应用上层代码生成的测试用例。 如上所述的验证软件的划分允许“分割域”验证模式，其中只有低级代码由模拟处理器模型执行，而其余代码在模拟器外部执行。 因为大多数验证软件在模拟器外部执行，而仅在模拟处理器上执行低级代码，所以执行高级功能的开销从模拟器中移除。 因此，启用更快的验证。
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7.发明授权Method for re-using system-on-chip verification software in an operating system 失效在操作系统中重新使用片上系统验证软件的方法公开(公告)号：US06868545B1
公开(公告)日：2005-03-15
申请号：US09495236
申请日：2000-01-31
CPC分类号： G06F17/5045 , G06F2217/86
摘要： The time, effort and expense required to develop verification software for testing and de-bugging system-on-chip (SOC) designs represents a considerable investment. According to the method of the present invention, a portion of such verification software may be re-used in an operating system (OS) (i.e., a system used for, e.g., general business, technical or scientific applications as opposed to software testing) to capitalize on the investment.The verification software includes low-level device drivers (LLDDs) which were coded for and paired with specific device designs (“cores”) throughout the verification process, and were consequently also verified (i.e., de-bugged) in the process. Thus, the low-level device drivers represent reliable software with detailed knowledge of the corresponding devices.By developing a thin middle-level device driver layer of software to interface between a particular OS and the lower-level device drivers, the LLDDs can be re-used in an OS that uses devices that the LLDDs were designed for. This frees SOC customers from having to develop low-level software and instead allows them to concentrate on developing their particular applications, or “value-added” software.
摘要翻译： 开发用于测试和解除系统级芯片（SOC）设计的验证软件所需的时间，精力和费用代表了相当大的投资。 根据本发明的方法，这种验证软件的一部分可以在操作系统（OS）（即，用于例如一般业务，技术或科学应用而不是软件测试的系统）中被重新使用， 验证软件包括在整个验证过程中编码并与特定设备设计（“核心”）配对的低级设备驱动程序（LLDD），并因此也被验证（即删除） 正在进行中。 因此，低级设备驱动程序表示可靠的软件，具有相应设备的详细知识。通过开发薄型的中间级设备驱动程序软件层，可以在特定的操作系统和下级设备驱动程序之间进行接口，LLDD可以重新 - 在使用LLDD设计的设备的操作系统中使用。 这样可以让SOC客户不必开发低级软件，而是让他们专注于开发其特定应用程序或“增值”软件。
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公开(公告)号：US06571373B1
公开(公告)日：2003-05-27
申请号：US09494565
申请日：2000-01-31
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method for communicating with and controlling design logic modules (“cores”) external to a system-on-chip (SOC) design during verification of the design uses verification software to generate and apply test cases to stimulate components of an SOC design in simulation; the results are observed and used to de-bug the design. Typically, SOC designs interface with cores that are external to the design. Existing methods of including such external cores in a verification test of a SOC design typically entail having to create special test cases to control the external cores; such test cases typically do not communicate with test cases being applied internally to the SOC and therefore lack realism. An external memory-mapped test device (EMMTD) according to the present invention is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal EMMTD logic provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus. In one embodiment, a test case being executed by a simulator embedded processor in the SOC can communicate with and control elements external to the SOC, by using the EMMTD to perform such functions as initiating external core logic which drives test signals to an internal core, directly controlling an internal core via its external interface, or determining the status of an external core.
摘要翻译： 在验证设计期间，与系统级芯片（SOC）设计外部的设计逻辑模块（“核心”）进行通信和控制的方法使用验证软件来生成和应用测试用例以刺激模拟中的SOC设计的组件 ; 观察结果并用于对设计进行设计。 通常，SOC设计与设计外部的核心相连接。 在SOC设计的验证测试中包括这些外部核心的现有方法通常需要创建专门的测试用例来控制外部核心; 这种测试用例通常不会与内部应用于SOC的测试用例进行通信，因此缺乏现实感。 根据本发明的外部存储器映射测试设备（EMMTD）耦合在被仿真中测试的SOC设计和SOC设计外部的核心之间。 内部EMMTD逻辑通过启用包括总线上的驱动数据，读取总线上的数据的当前状态以及捕获总线上的正向和负向边沿转换的功能，提供耦合到EMMTD双向总线的外部核心的控制和状态监视 总线。 在一个实施例中，由SOC中的模拟器嵌入式处理器执行的测试用例可以通过使用EMMTD执行诸如启动将测试信号驱动到内部核心的外部核心逻辑的功能来与SOC外部的元件进行通信和控制， 通过其外部接口直接控制内部核心，或者确定外部核心的状态。
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