METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE
    2.
    发明申请
    METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE 失效
    使用镜像界面进行逻辑验证的方法和系统

    公开(公告)号:US20080222583A1

    公开(公告)日:2008-09-11

    申请号:US11930820

    申请日:2007-10-31

    IPC分类号: G06F17/50 G01R31/00

    摘要: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

    摘要翻译: 核心系统芯片(SOC)外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常,标准化模型提供比所需更多的功能。 可以开发和利用测试模型,而不是标准化模型,但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用,以验证外部接口。 因为可以利用所有接口I / O连接,因此提供了验证这种接口的成本有效且高可重复使用的方式。

    Method and system for logic verification using mirror interface
    3.
    发明授权
    Method and system for logic verification using mirror interface 失效
    使用镜像接口进行逻辑验证的方法和系统

    公开(公告)号:US07729877B2

    公开(公告)日:2010-06-01

    申请号:US11930820

    申请日:2007-10-31

    IPC分类号: G01R31/00 G01R31/14

    摘要: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

    摘要翻译: 核心系统芯片(SOC)外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常,标准化模型提供比所需更多的功能。 可以开发和利用测试模型,而不是标准化模型,但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用,以验证外部接口。 因为可以利用所有接口I / O连接,因此提供了验证这种接口的成本有效且高可重复使用的方式。

    Method and system for logic verification using mirror interface
    4.
    发明授权
    Method and system for logic verification using mirror interface 有权
    使用镜像接口进行逻辑验证的方法和系统

    公开(公告)号:US07353131B2

    公开(公告)日:2008-04-01

    申请号:US10986773

    申请日:2004-11-15

    IPC分类号: G01R31/00 G01R31/14

    摘要: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

    摘要翻译: 核心系统芯片(SOC)外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常,标准化模型提供比所需更多的功能。 可以开发和利用测试模型,而不是标准化模型,但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用,以验证外部接口。 因为可以利用所有接口I / O连接,因此提供了验证这种接口的成本有效且高可重复使用的方式。