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公开(公告)号：US20130212549A1
公开(公告)日：2013-08-15
申请号：US13529601
申请日：2012-06-21
申请人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
发明人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.
摘要翻译： 通过对标准单元布局的可路由特性进行优先级来创建标准单元的布局。 可布线性特征被优先化，使得在单元格布局中强调更有可能提高路由效率的特性。 路由特性的优先级可以由一组权重指示，集合中的每个权重指示标准信元布局的对应可路由特性的优先级。 权重可用于计算标准单元的可路由特性的加权和，从而提供有效地比较不同标准单元布局的可布线性的方式。
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公开(公告)号：US08978004B2
公开(公告)日：2015-03-10
申请号：US13529601
申请日：2012-06-21
申请人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
发明人： Robert L. Maziasz , Alexander L. Kerre , Vladimir P. Rozenfeld , Mikhail A. Sotnikov , Igor G. Topouzov
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.
摘要翻译： 通过对标准单元布局的可路由特性进行优先级来创建标准单元的布局。 可布线性特征被优先化，使得在单元格布局中强调更有可能提高路由效率的特性。 路由特性的优先级可以由一组权重指示，集合中的每个权重指示标准信元布局的对应可路由特性的优先级。 权重可用于计算标准单元的可路由特性的加权和，从而提供有效地比较不同标准单元布局的可布线性的方式。
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公开(公告)号：US20080092100A1
公开(公告)日：2008-04-17
申请号：US11811407
申请日：2007-06-11
申请人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
发明人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.
摘要翻译： 提供了一种方法，数据处理系统和计算机程序产品，用于多次路由电路布局，导致多个路由。 为每个路由计算电迁移质量值，并选择具有最佳电迁移质量值的路由。 在一个实施例中，分析每个路由，注意通过每个路由段的电流，以便计算用于计算路由质量向量的当前分布。 在另一个实施例中，生成多个布局，并且针对具有选择了最佳电迁移质量向量的位置的各种布局来计算电迁移放置质量向量。 在一个实施例中，具有最佳电迁移质量矢量的布置被路由多次以确定具有最低（最佳）电迁移质量值的路由。
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公开(公告)号：US07721245B2
公开(公告)日：2010-05-18
申请号：US11811407
申请日：2007-06-11
申请人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
发明人： Robert L. Maziasz , Vladimir P. Rozenfeld , Iouri Smirnov , Sergei V. Somov , Igor G. Topouzov , Lyudmila Zinchenko
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.
摘要翻译： 提供了一种方法，数据处理系统和计算机程序产品，用于多次路由电路布局，导致多个路由。 为每个路由计算电迁移质量值，并选择具有最佳电迁移质量值的路由。 在一个实施例中，分析每个路由，注意通过每个路由段的电流，以便计算用于计算路由质量向量的当前分布。 在另一个实施例中，生成多个布局，并且针对具有选择了最佳电迁移质量向量的位置的各种布局来计算电迁移放置质量向量。 在一个实施例中，具有最佳电迁移质量矢量的布置被路由多次以确定具有最低（最佳）电迁移质量值的路由。
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公开(公告)号：US20120159412A1
公开(公告)日：2012-06-21
申请号：US13398177
申请日：2012-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.
摘要翻译： 布局工具部分地复制基本单元格的布局以确定目标单元格的布局。 基本单元是表示具有确定的布局的一组晶体管的布置的信息。 目标单元是指示另一组晶体管的期望布置的信息。 布局工具识别基本单元晶体管的子集与目标单元晶体管的子集之间的对应关系，并复制所识别的基本单元子集的布局，以确定所识别的目标单元子集的布局。 此外，布局工具可以识别与目标细胞子集紧密匹配的基细胞子集，但由于靶细胞子集中的障碍，布局不能精确复制。 对于这样确定的基本单元子集，布局工具可以通过调整基本单元子集布局来确定布局，以避免障碍。
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公开(公告)号：US08726218B2
公开(公告)日：2014-05-13
申请号：US13398177
申请日：2012-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.
摘要翻译： 布局工具部分地复制基本单元格的布局以确定目标单元格的布局。 基本单元是表示具有确定的布局的一组晶体管的布置的信息。 目标单元是指示另一组晶体管的期望布置的信息。 布局工具识别基本单元晶体管的子集与目标单元晶体管的子集之间的对应关系，并复制所识别的基本单元子集的布局，以确定所识别的目标单元子集的布局。 此外，布局工具可以识别与目标细胞子集紧密匹配的基细胞子集，但由于靶细胞子集中的障碍，布局不能精确复制。 对于这样确定的基本单元子集，布局工具可以通过调整基本单元子集布局来确定布局，以避免障碍。
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