公开(公告)号：US20050257109A1

公开(公告)日：2005-11-17

申请号：US10630480

申请日：2003-07-29

申请人： Roberto Averbuj ,  David Hansquine

发明人： Roberto Averbuj ,  David Hansquine

IPC分类号： G11C29/16 ,  G01R31/28

CPC分类号： G11C29/16

摘要： A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

摘要翻译： 描述了具有分布式算法解释的内置自检（BIST）架构。 该架构包括三层抽象层次：集中式BIST控制器，一组排序器和一组存储器接口。 BIST控制器存储一组命令，通常定义用于测试存储器模块的算法，而不考虑存储器模块的物理特性或时序要求。 顺控程序根据命令协议解释命令并生成序列的存储器操作。 存储器接口根据存储器模块的物理特性将存储器操作应用于存储器模块，例如通过基于存储器模块的行列排列来转换地址和数据信号，以实现由命令描述的位模式。 命令协议允许以非常简洁的方式描述强大的算法，其可以应用于具有不同特征的存储器模块。