公开(公告)号：US5029133A

公开(公告)日：1991-07-02

申请号：US575086

申请日：1990-08-30

申请人： Ross V. La Fetra ,  Lee Fleming

发明人： Ross V. La Fetra ,  Lee Fleming

IPC分类号： G01R31/3185

CPC分类号： G01R31/318572

摘要： An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.

摘要翻译： 公开了一种改进的集成电路芯片设计，其更适合于使用现有的电路测试器进行测试。 该芯片包括并行加载指令，可减少加载内部扫描寄存器所需的测试仪内存的字数。 并行加载指令加载连接到芯片的输入引脚的存储单元，然后将其移入扫描寄存器。