公开(公告)号：US5029133A

公开(公告)日：1991-07-02

申请号：US575086

申请日：1990-08-30

申请人： Ross V. La Fetra ,  Lee Fleming

发明人： Ross V. La Fetra ,  Lee Fleming

IPC分类号： G01R31/3185

CPC分类号： G01R31/318572

摘要： An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.

摘要翻译： 公开了一种改进的集成电路芯片设计，其更适合于使用现有的电路测试器进行测试。 该芯片包括并行加载指令，可减少加载内部扫描寄存器所需的测试仪内存的字数。 并行加载指令加载连接到芯片的输入引脚的存储单元，然后将其移入扫描寄存器。

公开(公告)号：US07076686B2

公开(公告)日：2006-07-11

申请号：US10079988

申请日：2002-02-20

申请人： Ross V. La Fetra

发明人： Ross V. La Fetra

IPC分类号： G06F11/08 ,  G06F11/20

CPC分类号： G11C7/20

摘要： A method of hot swapping memory is described. A memory system includes a plurality of memory banks such that a memory word is divided into the memory banks. The memory system is provided a spare memory bank. One of the memory banks is selected to be replaced. The memory system is configured to perform write operations associated with the selected memory bank to both the selected and spare memory banks. Atomic read and write operations are performed such that the content of the selected memory bank is copied to the spare memory bank. The memory system is subsequently configured to redirect operations to be performed on the selected memory bank to the spare memory bank such that the selected memory bank can be hot replaced.

摘要翻译： 描述热插拔存储器的方法。 存储器系统包括多个存储器组，使得存储器字被分成存储体。 存储器系统提供有备用存储体。 其中一个存储体被选择被替换。 存储器系统被配置为执行与选择的存储体相关联的写入操作到所选择的和备用的存储体。 执行原子读和写操作，使得所选择的存储体的内容被复制到备用存储体。 存储器系统随后被配置为将要在所选择的存储体上执行的操作重定向到备用存储体，使得所选择的存储体可以被热替换。

公开(公告)号：US07016213B2

公开(公告)日：2006-03-21

申请号：US10842297

申请日：2004-05-10

申请人： Richard W. Reeves ,  Ross V. La Fetra ,  Paul C. Miranda

发明人： Richard W. Reeves ,  Ross V. La Fetra ,  Paul C. Miranda

IPC分类号： G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A host is coupled to a serially connected chain of memory modules. In one embodiment, a method for initializing the host and each of memory modules includes the host transmitting a first synchronization pattern and a second synchronization pattern downstream in response to a reset condition. The method also includes each memory module in the serially connected chain of memory modules receiving and forwarding the first and the second synchronization pattern. Each memory module receives and forwards the first and the second synchronization pattern. Further, the method includes the host transmitting a plurality of NOP packets downstream in response to transmitting the second synchronization pattern. Lastly, the method includes a portion of the memory modules injecting and transmitting NOP packets upstream in response to receiving the second synchronization pattern from downstream.

摘要翻译： 主机耦合到串行连接的存储器模块链。 在一个实施例中，用于初始化主机和每个存储器模块的方法包括主机响应于复位条件向下游发送第一同步模式和第二同步模式。 该方法还包括串行连接的存储器模块链中的每个存储器模块接收和转发第一和第二同步模式。 每个存储器模块接收并转发第一和第二同步模式。 此外，该方法包括主机响应于发送第二同步模式向下游发送多个NOP分组。 最后，该方法包括一部分存储器模块响应于从下游接收第二同步模式而向上游注入和发送NOP分组。

公开(公告)号：US06990539B2

公开(公告)日：2006-01-24

申请号：US10122986

申请日：2002-04-15

申请人： Ross V. La Fetra ,  Peter M. Arnold

发明人： Ross V. La Fetra ,  Peter M. Arnold

IPC分类号： G06F13/00 ,  G06F13/368 ,  G06F13/37

CPC分类号： G06F13/364 ,  G06F15/177

摘要： An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching stage coupled to the bus and configured to select a first route configuration if two processors are coupled to the bus. The switching stage is also configured to select a second route configuration if more that two processors are coupled to the bus. The switching stage determines if two or more processors are coupled to the bus. A logic block may be used to determine the required configuration based on the detected processor population. A method of changing bus request routing to allow functionality with 2 way or 4 way processors, includes: detecting if a dual processor arrangement or a multi-processor arrangement is coupled to a bus; and selecting a first route configuration if a dual processor arrangement is coupled to the bus and selecting a second route configuration if a multi-processor arrangement is coupled to the bus.

摘要翻译： 一种用于实现总线请求路由以允许具有2路或4路处理器的功能的装置，包括被配置为提供总线请求路由的总线; 以及总线请求路由交换阶段，其耦合到总线并且被配置为如果两个处理器耦合到总线则选择第一路由配置。 如果更多的两个处理器耦合到总线，则切换级还被配置为选择第二路由配置。 切换阶段确定两个或多个处理器是否耦合到总线。 可以使用逻辑块来基于检测到的处理器群来确定所需的配置。 一种改变总线请求路由以允许具有2路或4路处理器的功能的方法，包括：检测双处理器布置或多处理器布置是否耦合到总线; 以及如果双处理器布置耦合到所述总线并且如果多处理器布置耦合到总线则选择第二路由配置，则选择第一路由配置。

公开(公告)号：US08589670B2

公开(公告)日：2013-11-19

申请号：US12413147

申请日：2009-03-27

申请人： Ross V. La Fetra

发明人： Ross V. La Fetra

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F9/24 ,  G06F13/00

CPC分类号： G06F11/3409 ,  G06F2201/81

摘要： A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating point of at least one operational characteristic of the system and a first margin associated therewith. The first margin is compared to a predetermined threshold margin and if the first margin is less than the predetermined threshold margin, the configuration of the system is adjusted to provide a configuration with greater margin for the operational characteristic. The system is retrained with the new configuration to determine a second operating point and a second margin associated therewith and compares the second margin to the threshold margin to determine if the second margin is more than the threshold margin, to satisfy reliability requirements.

摘要翻译： 系统提供了一种通过允许评估边距来增加可靠性的机制，并且如果当前配置的一个或多个边距太小，则修改系统配置以增加边距。 计算设备通过训练来确定系统的至少一个操作特性的第一操作点和与其相关联的第一余量。 将第一余量与预定阈值余量进行比较，并且如果第一余量小于预定阈值余量，则调整系统的配置以为操作特性提供更​​大余量的配置。 用新的配置重新训练系统以确定与之相关联的第二操作点和第二余量，并将第二余量与阈值余量进行比较，以确定第二余量是否大于阈值余量，以满足可靠性要求。

公开(公告)号：US20100250915A1

公开(公告)日：2010-09-30

申请号：US12413147

申请日：2009-03-27

申请人： Ross V. La Fetra

发明人： Ross V. La Fetra

IPC分类号： G06F9/00 ,  G06F19/00

CPC分类号： G06F11/3409 ,  G06F2201/81

摘要： A system provides a mechanism for increasing reliability by allowing margins to be evaluated and if one or more margins of a current configuration are too small, system configuration is modified to increase the margin. A computing device determines through training a first operating point of at least one operational characteristic of the system and a first margin associated therewith. The first margin is compared to a predetermined threshold margin and if the first margin is less than the predetermined threshold margin, the configuration of the system is adjusted to provide a configuration with greater margin for the operational characteristic. The system is retrained with the new configuration to determine a second operating point and a second margin associated therewith and compares the second margin to the threshold margin to determine if the second margin is more than the threshold margin, to satisfy reliability requirements.

摘要翻译： 系统提供了一种通过允许评估边距来增加可靠性的机制，并且如果当前配置的一个或多个边距太小，则修改系统配置以增加边距。 计算设备通过训练来确定系统的至少一个操作特性的第一操作点和与其相关联的第一余量。 将第一余量与预定阈值余量进行比较，并且如果第一余量小于预定阈值余量，则调整系统的配置以为操作特性提供更​​大余量的配置。 用新的配置重新训练系统以确定与之相关联的第二操作点和第二余量，并将第二余量与阈值余量进行比较，以确定第二余量是否大于阈值余量，以满足可靠性要求。

公开(公告)号：US5509119A

公开(公告)日：1996-04-16

申请号：US311478

申请日：1994-09-23

申请人： Ross V. La Fetra

发明人： Ross V. La Fetra

IPC分类号： G06F12/08 ,  G06F11/10 ,  G06F12/16 ,  G06F11/34

CPC分类号： G06F11/1064 ,  G06F11/1044

摘要： A fast cache hit detection method and apparatus. The present invention provides a method and apparatus for quickly determining whether there is a cache hit in cache memory systems utilizing error corrected tags. The hit detection process is split into two paths. The first path includes a circuit to check and correct a tag stored in the cache memory. The second path tests the validity of the tag stored in the cache memory by computing the appropriate ECC information using memory address information supplied by the computer CPU and comparing the tag and ECC stored in the cache memory to the CPU address and computed ECC. As the computed ECC is performed in parallel with the cache RAM access, this second path provides hit confirmation faster than the first path which must process the tag and ECC stored in the cache RAM through a ECC check and correction circuit. If a fast hit is confirmed, then the cache memory system can proceed to supply cache data to the CPU. If a fast hit is not confirmed, then the cache memory system waits for the first path to check and correct, if required, the tag stored in the cache and then test the corrected tag. As the cache tag typically does not need correction and most cache systems have a high hit rate, this invention dramatically increases the efficiency of the cache memory system.

摘要翻译： 一种快速缓存命中检测方法和装置。 本发明提供了一种方法和装置，用于使用纠错标签快速确定高速缓冲存储器系统中是否存在高速缓存命中。 命中检测过程分为两个路径。 第一路径包括检查和校正存储在高速缓冲存储器中的标签的电路。 第二路径通过使用由计算机CPU提供的存储器地址信息计算适当的ECC信息来测试存储在高速缓冲存储器中的标签的有效性，并将存储在高速缓冲存储器中的标签和ECC与CPU地址和计算的ECC进行比较。 当计算出的ECC与高速缓存RAM访问并行执行时，该第二路径比通过ECC检查和校正电路必须处理存储在高速缓存RAM中的标签和ECC的第一路径提供命中确认。 如果确定了快速命中，则缓存存储器系统可以继续向CPU提供高速缓存数据。 如果没有确认快速命中，则高速缓冲存储器系统等待第一路径检查并根据需要校正存储在高速缓存中的标签，然后测试校正的标签。 由于缓存标签通常不需要校正，并且大多数缓存系统具有高命中率，所以本发明显着提高了高速缓冲存储器系统的效率。

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：US5155828A

公开(公告)日：1992-10-13

申请号：US810523

申请日：1991-12-17

申请人： Ross V. La Fetra ,  John F. Shelton

发明人： Ross V. La Fetra ,  John F. Shelton

IPC分类号： G06F12/08

CPC分类号： G06F12/0897

摘要： A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory. The processor then reads the data from the first cache memory. Generally, when the processor reads data from the first cache memory, the read data is written into the second cache memory.

摘要翻译： 计算系统包括处理器，包含由处理器使用的数据和两个高速缓冲存储器的系统存储器。 每个缓存存储器直接连接到处理器。 第一缓存存储器连接到处理器和系统存储器。 第一个缓存存储器包含系统内存中的数据子集。 第二高速缓存存储器也连接到处理器。 第二缓存存储器包含第一高速缓冲存储器中的数据子集。 仅使用第一个高速缓冲存储器来维护系统内存中的数据完整性。 每当处理器写入数据时，处理器将数据都写入第一高速缓冲存储器和第二高速缓冲存储器。 每当处理器读取数据时，处理器尝试从第二高速缓冲存储器读取数据。 如果在第二高速缓存存储器中存在未命中，则处理器尝试从第一高速缓冲存储器读取数据。 如果在第一缓存存储器中存在缺失，则从系统存储器检索数据并将其放置在第一缓存存储器中。 然后处理器从第一高速缓冲存储器读取数据。 通常，当处理器从第一高速缓冲存储器读取数据时，将读取的数据写入第二高速缓冲存储器。