摘要:
A method for operating a railway section that includes section elements, which are each actuated by a processor that is reliable in terms of signaling and cyclically carries out a test routine. A railway section is configured for carrying out the method. In order to save energy and cost, the processor is operated selectively in active mode or sleep mode. From the sleep mode the processor is switched to the active mode for the duration of the test routine by way of a timer logic element that is reliable in terms of signaling.
摘要:
A light signal device includes at least one light sensor and a signal generator which has a light source and a shutter disk. An inner side of a screening stop, which protects the shutter disk, holds at least one reflector element which reflects a portion of the light emitted by the light source in the direction of the at least one light sensor. A method for ascertaining the degree of soiling of a shutter disk for a signal generator is also provided.
摘要:
A circuit for driving and monitoring a light signal, in particular an LED signal, has an actuating part for outputting a process voltage, and a signal transmitter for setting current windows for daytime operation and nighttime operation. In order to achieve a high degree of independence between the circuit and variable parameters, in particular the power consumption of the lighting elements, the signal transmitter has a regulator which is connected to the monitoring logic via brightness sensors for measurement of the brightness of the light signal, with the monitoring logic producing a daytime or nighttime nominal value of the current window for the regulator.
摘要:
A method for operating a railway section that includes section elements, which are each actuated by a processor that is reliable in terms of signaling and cyclically carries out a test routine. A railway section is configured for carrying out the method. In order to save energy and cost, the processor is operated selectively in active mode or sleep mode. From the sleep mode the processor is switched to the active mode for the duration of the test routine by way of a timer logic element that is reliable in terms of signaling.