公开(公告)号：US06789186B1

公开(公告)日：2004-09-07

申请号：US09507038

申请日：2000-02-18

申请人： Russell C. Brockmann ,  Kevin David Safford ,  Jane Wang ,  Chris Poirier

发明人： Russell C. Brockmann ,  Kevin David Safford ,  Jane Wang ,  Chris Poirier

IPC分类号： G06G900

CPC分类号： G06F9/3804 ,  G06F9/30174

摘要： A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

摘要翻译： 提供了一种方法和装置，用于提高宏指令转换成相应微指令的速率。 编码被添加到微代码存储设备中。 编码指示微指令流将以确定的周期数结束。 循环数由在不使用流量长度预测的情况下将被引入的处理流水线中的取消指令的数量来确定。 对于小于一定数量的循环的流量长度，在入口点结构中使用提示位。 对于大于确定长度的流量长度，提示位在微指令流的末尾的第三行编码。 使用这种方法，可以暗示任何长度的流。 此外，也可以暗示不源于入口点结构的流。 该方法减少了入口点结构中所需的提示位的数量，并提供了更好的预测。

公开(公告)号：US20120171116A1

公开(公告)日：2012-07-05

申请号：US13191160

申请日：2011-07-26

申请人： Bruce Edward Tomczuk ,  Gary Lee Olson ,  Richard Scott Pottorf ,  Jane Wang ,  Bhaskara Rao Nallaganchu

发明人： Bruce Edward Tomczuk ,  Gary Lee Olson ,  Richard Scott Pottorf ,  Jane Wang ,  Bhaskara Rao Nallaganchu

IPC分类号： A61K31/69 ,  A61K51/04 ,  A61K49/10 ,  A61K49/04 ,  A61K49/22 ,  A61P9/10 ,  A61P9/12 ,  A61P9/00 ,  A61P11/06 ,  A61P11/00 ,  A61P7/02 ,  A61P31/00 ,  A61P35/00 ,  A61P17/02 ,  A61P1/00 ,  A61P15/00 ,  A61P37/00 ,  A61P15/06 ,  A61P17/06 ,  A61P29/00 ,  A61P31/04 ,  A61P37/02 ,  C07F5/02

CPC分类号： C07F5/025 ,  A61K31/69 ,  A61K49/0004 ,  A61K51/044 ,  C07F5/02 ,  C07J43/003 ,  Y02A50/411

摘要： The present invention includes arginase enzyme inhibitors, compositions comprising these arginase inhibitors, and methods of treating or diagnosing conditions characterized either by abnormally high arginase activity or abnormally low nitric oxide levels in a mammal, comprising administering compositions of the invention to the mammal.

摘要翻译： 本发明包括精氨酸酶抑制剂，包含这些精氨酸酶抑制剂的组合物，以及治疗或诊断以哺乳动物异常高的精氨酸酶活性或异常低的一氧化氮水平为特征的病症的方法，包括向哺乳动物施用本发明的组合物。

公开(公告)号：US20160219953A1

公开(公告)日：2016-08-04

申请号：US14609346

申请日：2015-01-29

申请人： Jane Wang

发明人： Jane Wang

IPC分类号： A41D15/04 ,  A41D3/00 ,  A47G9/08

CPC分类号： A41D15/04 ,  A41D3/00 ,  A47G9/06 ,  A47G9/086 ,  A47G2009/003

摘要： A composite jacket and sleeping bag apparatus for selective use as a jacket and a sleeping bag. The composite jacket and sleeping bag apparatus comprises a base jacket having an attached expandable hood and an inflatable air mattress pack. The base jacket is converted from a jacket configuration to a sleeping bag configuration by unzipping and opening it, unfolding both a fold out leg extension and a fold out top cover, and then connecting the sides of the fold out top cover to the sides of the opened base jacket and fold out leg extension, thereby forming a substantial enclosure in which a user can rest. In this configuration, the inflatable air mattress pack can be deployed to provide addition support to a user laying on the opened base jacket and fold out leg extension.

摘要翻译： 复合护套和睡袋设备，可选择用作夹克和睡袋。 复合护套和睡袋装置包括具有附接的可扩展罩和可充气空气床垫包的底座护套。 通过解开和打开底座外套，将其从外套配置转换为睡袋配置，展开折叠腿部延伸部和折叠顶盖，然后将折叠部分的顶部连接到顶盖的两侧 打开底座护套并折叠腿部延伸部，从而形成用户可以休息的实质的外壳。 在这种构造中，可膨胀充气式气垫组件可以对铺设在开放的底座上的用户提供额外的支撑并且折叠腿部延伸。

公开(公告)号：US4897805A

公开(公告)日：1990-01-30

申请号：US194832

申请日：1988-05-17

申请人： Jane Wang

发明人： Jane Wang

IPC分类号： G06T11/40

CPC分类号： G06T11/40

摘要： A method of filling a polygon as represented on a scan-line raster display includes storing data representative of the polygon edges, computing the points of intersection of a scan-line with each polygon edge, assigning a count having a parity value to each crossed-edge, and combining all colinear horizontal edges at the points of intersection. The number of polygon edges positioned above the colinear horizontal edge and which have a vertex coincident with the colinear horizontal edge, as well as the number of polygon edges positioned below the colinear horizontal edge and which have a vertex coincident with the colinear horizontal edge, are calculated. The parity of the crossed-edge count is inverted if the parity of both the above edge count and below edge count are even, and the string of pixels along the raster display scan-line from the current edge intersection to the next edge intersection are modified if the parity of the crossed-edge count is odd.

摘要翻译： 如扫描线光栅显示器所示的填充多边形的方法包括存储表示多边形边缘的数据，计算扫描线与每个多边形边缘的交点，将具有奇偶校验值的计数分配给每个交叉 - 边缘，并且在交叉点处组合所有共线水平边缘。 位于共线水平边缘上方并且具有与共线水平边缘重合的顶点以及位于共线水平边缘下方并且具有与共线水平边缘重合的顶点的多边形边缘的数量的多边形边缘的数量是 计算。 如果上述边缘计数和下边缘计数的奇偶性均为偶数，则交叉边缘计数的奇偶校验被反转，并且沿着光栅显示从当前边缘交点到下一个边缘交点的扫描线的像素串被修改 如果交叉边数的奇偶校验是奇数。

公开(公告)号：USD576100S1

公开(公告)日：2008-09-02

申请号：US29263976

申请日：2006-08-02

申请人： Jane Wang

设计人： Jane Wang

公开(公告)号：US07359430B2

公开(公告)日：2008-04-15

申请号：US10156355

申请日：2002-05-28

申请人： John G. McDonough ,  Jane Wang ,  Yan Hui

发明人： John G. McDonough ,  Jane Wang ,  Yan Hui

IPC分类号： H04B1/00

CPC分类号： H04B1/707 ,  H04J13/004

摘要： A demodulator such as a Fast Hadamard Transform (FHT) based demodulator is used to demodulate all channels in a code space with code length equal to the data channel code. Since the codes for overhead control channels are usually longer, the control channel data is only partially uncovered. Once the necessary further processing is performed and the information to fully uncover the control channels is available, the control channel data is fully demodulated. By only processing one partially uncovered secondary control channel, the present invention reduces the implementation complexity. A hardware implementation of the above method, requires fewer data processing operations, and reduces data processing delays, resulting in lower power consumption.

摘要翻译： 解调器例如基于快速Hadamard变换（FHT）的解调器被用来解码码长度等于数据信道码的码空间中的所有信道。 由于开销控制信道的代码通常较长，因此控制信道数据仅部分被覆盖。 一旦执行必要的进一步的处理，并且完全发现控制信道的信息可用，则控制信道数据被完全解调。 通过仅处理一个部分未覆盖的辅助控制信道，本发明降低了实现的复杂度。 上述方法的硬件实现需要更少的数据处理操作，并减少数据处理延迟，从而降低功耗。

公开(公告)号：US07336640B2

公开(公告)日：2008-02-26

申请号：US10370352

申请日：2003-02-19

申请人： John G. McDonough ,  Jane Wang

发明人： John G. McDonough ,  Jane Wang

IPC分类号： H04J13/00

CPC分类号： H04J13/0048 ,  H04B1/707 ,  H04B2201/70707

摘要： A CDMA receiver (500) minimizes the use of hardware by taking advantage of the fact that Walsh sequences of a predetermined length (e.g., 16) are comprised of inverted and non-inverted versions of smaller length (e.g., 4) sequences. The receiver (500) performs the necessary uncovering operations for example of a Walsh sequence of length 16 by performing uncovering operations using smaller length Walsh sequences such as of length 4 and then performing subsequent summing operations with inverted and non-inverted versions of the results of such uncovering operations.

摘要翻译： CDMA接收机（500）通过利用预定长度（例如，16）的沃尔什序列由更小长度（例如，4）序列的反相和非反相版本组成的事实来最小化硬件的使用。 接收器（500）通过使用诸如长度为4的较小长度的沃尔什序列执行展开操作来执行例如长度为16的沃尔什序列的必要的发现操作，然后使用倒数和非反转版本的结果进行后续求和操作 这样的发现操作。

公开(公告)号：US07295632B2

公开(公告)日：2007-11-13

申请号：US10392511

申请日：2003-03-20

申请人： John G. McDonough ,  Jane Wang ,  Gibong Jeong ,  Der-Chieh Koon

发明人： John G. McDonough ,  Jane Wang ,  Gibong Jeong ,  Der-Chieh Koon

IPC分类号： H04L27/06

CPC分类号： H04L1/0071 ,  H04B7/2643 ,  H04L1/0045 ,  H04L1/0068

摘要： System and method for decoding punctured subframes. A preferred embodiment comprises a first deinterleaver unit (for example, 5-ms deinterleaver 502) and a second deinterleaver unit (for example, 20-ms deinterleaver 504) operating in parallel, deinterleaving one symbol stream using 5- and 20-ms duration frame formats, for example. After the reception of each 5-ms subframe, the subframe is decoded in a decode unit (for example, rate matching, decoding, and CRC checking (RDC) unit 530) to verify that the subframe contains 5 ms duration frame data. If so, the subframe is noted. If all 5-ms subframes in a 20-ms duration frame contain 5-ms duration data, no decoding of results by the second deinterleaver unit is needed. If the entire 20-ms duration frame is not all 5-ms duration data, then the 5-ms duration data subframes are zeroed and the remaining data is decoded as 20-ms duration data.

摘要翻译： 用于解码穿孔子帧的系统和方法。 优选实施例包括并行操作的第一解交织器单元（例如，5ms解交织器502）和第二解交织器单元（例如，20ms解交织器504），使用5和20ms持续时间帧解交织一个符号流 格式，例如。 在每个5ms子帧的接收之后，子帧在解码单元（例如，速率匹配，解码和CRC校验（RDC）单元530）中解码）以验证子帧包含5ms持续时间帧数据。 如果是，则注意子帧。 如果20毫秒持续时间帧中的所有5毫秒子帧都包含5毫秒持续时间数据，则不需要第二个解交织器单元对结果的解码。 如果整个20毫秒持续时间帧不是全部5毫秒持续时间数据，那么5毫秒持续时间数据子帧被归零，剩余的数据被解码为20毫秒持续时间数据。

公开(公告)号：US20060015660A1

公开(公告)日：2006-01-19

申请号：US10894208

申请日：2004-07-19

申请人： Kha Nguyen ,  William Wong ,  Mouluan Jang ,  Jane Wang

发明人： Kha Nguyen ,  William Wong ,  Mouluan Jang ,  Jane Wang

IPC分类号： G06F3/00

CPC分类号： G06F3/0605 ,  G06F3/0656 ,  G06F3/0676

摘要： A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer memory if there is no space in the buffer memory.

摘要翻译： 提供了一种用于维持耦合到存储控制器的缓冲存储器中的流量控制的方法。 存储控制器包括用于监视从缓冲存储器读取数据以及数据从缓冲存储器传送到主机的第一和第二计数器。 该方法包括：当数据放置在缓冲存储器中时，递增第一和第二计数器值; 当从缓冲存储器读取数据时递减第一计数器值; 并且当数据被发送到主机时递减第二计数器值。 该方法还包括：当缓冲存储器中没有数据时，暂停传输模块和存储盘之间的第一通道逻辑; 并且如果缓冲存储器中没有空间，则在盘和缓冲存储器之间暂停第二通道逻辑。

公开(公告)号：US06640270B1

公开(公告)日：2003-10-28

申请号：US09598262

申请日：2000-06-21

申请人： Jane Wang

发明人： Jane Wang

IPC分类号： G06F1312

CPC分类号： G06F1/18

摘要： A terminal connection box for connecting a computer and an external peripheral device. The terminal connection box comprises: a plurality of side walls forming a housing, an enhanced signal circuit located inside the housing for converting and boosting signals, a first cable connecting the enhanced signal circuit and the computer, and a 1394 type plug connecting the enhanced signal circuit and the external peripheral device. The 1394 type signals coming from the external peripheral device are boosted and converted by the enhanced signal circuit so as to be compatible to the computer. Signals coming from the computer are boosted and converted into 1394 type signals by the enhanced signal circuit so as to be compatible to the external peripheral device. Such that the external peripheral device and the computer can perform bi-directional intercommunications with their signal boosted by the enhanced signal circuit.

摘要翻译： 用于连接计算机和外部外围设备的终端连接盒。 端子接线盒包括：形成壳体的多个侧壁，位于壳体内部用于转换和升高信号的增强信号电路，连接增强信号电路和计算机的第一电缆以及连接增强信号的1394型插头 电路和外围设备。 来自外部外围设备的1394型信号由增强型信号电路升压和转换，以便与计算机兼容。 来自计算机的信号被增强信号电路提升并转换为1394型信号，以便与外部外围设备兼容。 使得外部外围设备和计算机可以通过增强信号电路提升的信号执行双向互通。