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公开(公告)号:US5416776A
公开(公告)日:1995-05-16
申请号:US250276
申请日:1994-05-27
CPC分类号: H04M11/06 , G06F13/409 , H04L27/00
摘要: An improved backplane apparatus for transmitting signals to and from a modem system. The modem system includes more than one modem for transmitting data via at least one telephone line and via at least one network. The modem system has a first bus for management signal communication with the modems at a predetermined first data rate, and a second bus for transmitting data between the telephone line and the modems at a predetermined second data rate greater than the first data rate. The modem system also has a third bus for transmitting data between the modems and the network at a predetermined third data rate greater than the second data rate, and a fourth bus for distributing DC power and ground potential. The modem system defines a first impedance for terminating the first bus, a second impedance for terminating the second bus, and a third impedance for terminating the third bus. Finally, the modem system has structure for spacing the busses in layers in the backplane dependent on the data rate of the bus, and a plurality of connector assemblies for interconnecting circuit boards with the busses. Each connector assembly comprises an array of connectors arranged in rows and columns. The connectors are coupled to the busses according to a predetermined pattern dependent on the data rate of the bus, whereby the number of connector assemblies coupled to the first, second and third busses can be increased.
摘要翻译: 用于向/从调制解调器系统发送信号的改进的背板装置。 调制解调器系统包括多于一个的调制解调器,用于经由至少一个电话线路和经由至少一个网络传输数据。 调制解调器系统具有用于以预定的第一数据速率与调制解调器进行管理信号通信的第一总线,以及用于以大于第一数据速率的预定的第二数据速率在电话线路和调制解调器之间传送数据的第二总线。 调制解调器系统还具有用于以大于第二数据速率的预定的第三数据速率在调制解调器和网络之间传送数据的第三总线,以及用于分配直流电力和地电位的第四总线。 调制解调器系统定义用于终止第一总线的第一阻抗,用于终止第二总线的第二阻抗和用于终止第三总线的第三阻抗。 最后,调制解调器系统具有取决于总线的数据速率的背板中的层间隔布局的结构,以及用于将电路板与总线互连的多个连接器组件。 每个连接器组件包括以行和列布置的连接器阵列。 连接器根据总线的数据速率根据预定模式耦合到总线,由此可以增加耦合到第一,第二和第三总线的连接器组件的数量。
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公开(公告)号:US09449458B2
公开(公告)日:2016-09-20
申请号:US14246215
申请日:2014-04-07
申请人: Russell C. Panzarella , John Burica , Scot Salzman
发明人: Russell C. Panzarella , John Burica , Scot Salzman
IPC分类号: G07F17/32
CPC分类号: G07F17/3223
摘要: The present invention relates to enabling an operating system software to selectively power cycle one or more components of a wagering gaming system comprising a central processing unit board having one or more central processing units, and one or more central processing unit components. The invention uses a memory comprising a dedicated power cycle control register, a power controller, and digital logic configured to initiate a power cycle of the one or more components of the wagering gaming machine when the operating system writes a predetermined value to the power cycle control register. Upon recognizing the predetermined value to a dedicated power cycle control register used solely for power cycling procedures, digital logic is initiated to terminate voltage supplied to the one or more components of the wagering gaming machine and restore power to the one or more components of the wagering gaming machine, effectively “cold booting” the selected one or more components of the wagering gaming machine main system board(s) without disrupting voltage supplied to the entirety of other components, including peripheral devices of the wagering gaming system.
摘要翻译: 本发明涉及使操作系统软件能够选择性地对循环游戏系统的一个或多个组件进行动力循环,所述游戏系统包括具有一个或多个中央处理单元的中央处理单元板以及一个或多个中央处理单元组件。 本发明使用包括专用功率周期控制寄存器,功率控制器和数字逻辑的存储器,其被配置为当操作系统将预定值写入功率周期控制时,启动投注游戏机的一个或多个组件的功率循环 寄存器。 在将专用功率循环控制寄存器识别为用于功率循环过程的预定值时,开始数字逻辑以终止提供给投注游戏机的一个或多个组件的电压,并将功率恢复到投注的一个或多个组件 游戏机,有效地“冷启动”投注游戏机主系统板的所选择的一个或多个组件,而不会中断提供给整个其他组件的电压,包括投注游戏系统的外围设备。
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