公开(公告)号：US07114142B1

公开(公告)日：2006-09-26

申请号：US10855667

申请日：2004-05-26

申请人： Russell Segal ,  Paul Rodman

发明人： Russell Segal ,  Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.

摘要翻译： 提供并描述了通过使用先前分层物理设计的物理设计信息来优化分层物理设计中的块的引脚的位置的方法。 在一个实施例中，确定当前集成电路的物理设计的每个块的针的多个位置的方法包括从现有集成电路的先前物理设计中检索物理设计信息。 物理设计信息包括路由拥塞模式。 继续地，基于路由拥塞简档向路由器提供多个约束。 然后，路由器用于执行用于为每个块生成引脚位置的顶级路由。 块的每个引脚在全局路由进入块的位置或全局路由退出块的位置处创建。