Circuit design apparatus, circuit design program, and circuit design method
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    发明申请
    Circuit design apparatus, circuit design program, and circuit design method 审中-公开
    电路设计装置,电路设计程序及电路设计方法

    公开(公告)号:US20070143726A1

    公开(公告)日:2007-06-21

    申请号:US11384344

    申请日:2006-03-21

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045 G06F2217/78

    摘要: There is provided a circuit design apparatus that performs logic design for realizing a reduction of power consumption and circuit simplification. A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines an insertion location of the clock gating circuit and reorganization of logical hierarchies based on the detected EN generation logic (S5), instructs logical hierarchy reorganization to be performed in logic synthesis (S8) and performs design change processing (S6). The apparatus performs logic synthesis based on RTL after design change and instruction of logical hierarchy reorganization (S10), and layouts a concrete circuit configuration (S12).

    摘要翻译: 提供了一种电路设计装置,其执行逻辑设计以实现功率消耗的降低和电路简化。 电路设计装置解释设计目标的RTL以执行其结构分析(S 2),基于结构分析的结果估计时钟门控的产生,检测EN生成逻辑(S 3)的RTL描述,并且检测 相同的EN生成逻辑(S 4)。 该装置基于检测到的EN生成逻辑(S 5)确定时钟选通电路的插入位置和逻辑层次的重新组合,指示在逻辑合成中执行逻辑层次重组(S 8),并进行设计变更处理(S 6 )。 该设备在设计改变和逻辑层次重组指令之后,基于RTL执行逻辑综合(S10),并布置了具体的电路配置(S12)。