公开(公告)号：US20120013403A1

公开(公告)日：2012-01-19

申请号：US13183101

申请日：2011-07-14

申请人： Ryusuke SAHARA ,  Satoshi UENO ,  Takahiro KAWATA

发明人： Ryusuke SAHARA ,  Satoshi UENO ,  Takahiro KAWATA

IPC分类号： H03F3/45

CPC分类号： H03G3/348 ,  H03F1/305 ,  H03F3/181 ,  H03F2200/411

摘要： An amplifier circuit is configured to be preceded by a single-ended-to-differential translate circuit using a BTL configuration operating at a low voltage and succeeded by amplifiers to amplify output signals VOT and VOB from the single-ended-to-differential translate circuit. The amplifier circuit activates a mute function of the subsequent amplifiers during state transition when the single-ended-to-differential translate circuit turns on. Consequently, the amplifier circuit fixes output signals OUTP and OUTN to 0 V and masks an output noise. The amplifier circuit inactivates the mute function after signals VOT and VOB become stable. Thereby, the amplifier circuit is capable of easily preventing a pop noise using a BTL configuration requested for high voltage output to drive a piezoelectric actuator.

摘要翻译： 放大器电路配置为在使用低电压工作的BTL配置的单端到差分平移电路之前，并由放大器继续放大来自单端到差分转换电路的输出信号VOT和VOB 。 当单端至差分平移电路导通时，放大器电路在状态转换期间激活后续放大器的静音功能。 因此，放大器电路将输出信号OUTP和OUTN固定为0V，并掩蔽输出噪声。 信号VOT和VOB变得稳定后，放大器电路使静音功能失效。 因此，放大电路能够容易地防止使用为高电压输出请求的BTL配置来驱动压电致动器。

公开(公告)号：US20080055140A1

公开(公告)日：2008-03-06

申请号：US11877561

申请日：2007-10-23

申请人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。