公开(公告)号：US20240340012A1

公开(公告)日：2024-10-10

申请号：US18624590

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BAEKMIN LIM ,  GYUSIK KIM ,  SEUNGJIN KIM ,  SEUNGHYUN OH

IPC: H03L7/081 ,  H03L7/093

CPC classification number: H03L7/081 ,  H03L7/093

Abstract: A clock generation device includes a delay line that generates a modulated clock signal from a reference clock signal having a first period, a pulse generator configured to receive the modulated clock signal and generate a pulse signal in response to edges of pulses included in the modulated clock signal, and a clock generator that generates a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal. The delay line generates a first pulse based on the reference clock signal and then generates a second pulse after a time modulated from the first period by a result of multiplying the second period by a first numerical value selected from a plurality of numerical values according to a certain probability.

公开(公告)号：US20240338049A1

公开(公告)日：2024-10-10

申请号：US18418856

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEGUN NOH ,  SEUNGHYUN OH ,  BAEKMIN LIM

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A deserializer includes a shift register circuit that outputs N output data by shifting input data based on a first clock signal, a clock divider that outputs N second clock signals N-divided from the first clock signal and having N phases different from each other, and outputs one or more third clock signal divided to have a frequency less than that of the second clock signals, a clock selecting circuit that outputs a selected clock signal having an edge corresponding to a second time after N number of clock cycles of the first clock signal have elapsed from a first time at which a valid period is detected in a selection signal for selecting the input data based on the N second clock signals and the one or more third clock signals, and a data align circuit that parallelizes the N output data based on the selected clock signal.