公开(公告)号：US20250165685A1

公开(公告)日：2025-05-22

申请号：US18952627

申请日：2024-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongnoh KIM ,  Suhyun CHAE ,  Dohan KIM ,  Younghoon SON ,  Jeeyong LEE ,  Insu CHOI

IPC: G06F30/32 ,  G06N3/12

Abstract: An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.