-
1.发明申请公开(公告)号：US20230130156A1
公开(公告)日：2023-04-27
申请号：US17512530
申请日：2021-10-27
发明人： Filippo M. MIATTO , Nicolas QUESADA
摘要： Embodiments described herein provide systems and methods for optimizing a Gaussian representation to design photonic circuits for preparing a given target quantum state. The systems and methods internally consider and optimize quantum representations (e.g., Gaussian transformations, Gaussian and non-Gaussian states). In some embodiments, the systems and methods may produce optimal Gaussian transformations or states. In some embodiments, the systems and methods extract circuit parameters from an optimal Gaussian transformation to produce quantum circuits or designs for generating the optimal states. Embodiments described herein relate to systems and methods for optimizing a Gaussian transformation for state generation.
-
公开(公告)号：US20220360427A1
公开(公告)日：2022-11-10
申请号：US17737480
申请日：2022-05-05
发明人： David Bruce COUSINS
摘要： Systems and methods for digital circuit emulation with homomorphic encryption include: receiving, by a hardware design tool chain, a customization file containing a predetermined set of one or more cells; converting, by the hardware design tool chain, a first digital circuit representation in a set of hardware design language (HDL) files into a second digital circuit representation based on the predetermined set of cells in the customization file; receiving, by an encrypted circuit emulator, a set of encrypted inputs; and executing, by the encrypted circuit emulator, the second digital circuit representation using the set of encrypted inputs to generate a set of encrypted outputs.
-
公开(公告)号：US20220284160A1
公开(公告)日：2022-09-08
申请号：US17574876
申请日：2022-01-13
申请人： GOODRICH CORPORATION
IPC分类号： G06F30/32
摘要： A method for controlling a PCBA data distributed ledger located on blockchain network and a system for implementing the method are disclosed. The method may comprise scanning, by an optical label reader, an optical label located on a PCB and decoding, by an entity device, the optical label. The method may further include receiving, by a ledger controller, a request to access a distributed ledger from the entity device; verifying, by the blockchain nodes, a public key received from the entity device; determining, by the ledger controller, whether a private key received from the entity device matches a stored login credential; and determining whether to allow the entity device to access at least a first block on the distributed ledger.
-
公开(公告)号：US11409931B1
公开(公告)日：2022-08-09
申请号：US17203497
申请日：2021-03-16
发明人： Jagjot Kaur , William Scott Gaskins
IPC分类号： G06F30/333 , G06F30/30 , G06F30/32 , G06F30/396 , G06F119/12 , G01R31/3185 , G01R31/317
摘要： A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.
-
公开(公告)号：US11378943B2
公开(公告)日：2022-07-05
申请号：US16496604
申请日：2018-03-26
发明人： Shintaro Kumano , Makoto Kishi , Keisuke Yamamoto , Katsuhiko Abe
IPC分类号： G05B19/41 , G06F30/15 , G06F30/17 , G06F30/18 , G06F30/20 , G06F30/32 , G06F30/34 , G05B19/418 , G06F119/00
摘要： In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.
-
公开(公告)号：US20220215147A1
公开(公告)日：2022-07-07
申请号：US17703181
申请日：2022-03-24
申请人： Intel Corporation
IPC分类号： G06F30/32 , G06F30/343
摘要： An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.
-
公开(公告)号：US11176300B2
公开(公告)日：2021-11-16
申请号：US16266043
申请日：2019-02-02
申请人： IRDETO B.V.
发明人： Gerard Johan Dekker
IPC分类号： G06F30/30 , H01L27/00 , G06F21/00 , G06F30/337 , H01L27/02 , G06F30/39 , G06F30/32 , G06F21/14 , G06F21/73 , G06F111/20
摘要： Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design. For each individualized processing chip the individualized processing chip design is provided for fabrication of the individualized processing chip according to the individualized processing chip design. The individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.
-
公开(公告)号：US20210334450A1
公开(公告)日：2021-10-28
申请号：US17365555
申请日：2021-07-01
申请人： quadric.io, Inc.
IPC分类号： G06F30/398 , G06F30/337 , G06F30/373 , G06F30/27 , G06F30/32
摘要： Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.
-
公开(公告)号：US20210116505A1
公开(公告)日：2021-04-22
申请号：US16992105
申请日：2020-08-13
申请人： Wenzhou University
发明人： Liang Shu , Dingfang Chen , Yanfang Yang , Guichu Wu , Ziran Wu , Wei Chen , Miao Yang , Jie Zhang , Xu Zhang
IPC分类号： G01R31/327 , G06F30/32 , H02H1/00
摘要： A digital-twin modeling method for an automated testing pipeline for circuit breakers involves acquiring a three-dimensional digitalized model of each mechanical installation in the testing pipeline; modeling hierarchy according to an actual production process and motion states; performing mesh optimization on the resulting model; designing movements of each said mechanical installation, so as to obtain mechanical movement tracks of the models; combining actual movement logic and cooperative relationship among the movements to edit the mechanical movement tracks of the models; and introducing motion control, so as to conduct motion simulation in a digital-twin scene, thereby implementing virtual movements synchronous with movements of the actual testing pipeline. The method realizes centralized management of production data of the pipeline and realizes remote visualized operation, management and maintenance of the testing pipeline, thereby providing a basic platform for digitalized production of miniature circuit breakers.
-
公开(公告)号：US20200326534A1
公开(公告)日：2020-10-15
申请号：US16913490
申请日：2020-06-26
摘要： A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.042 秒)