公开(公告)号：US20180374540A1

公开(公告)日：2018-12-27

申请号：US15881208

申请日：2018-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Gyung HWANG ,  Byoung Taek KIM ,  Yong Seok KIM ,  Ju Seok LEE

IPC: G11C16/12 ,  G11C16/08

Abstract: A memory device includes a memory cell array including a first switch cell, a second switch cell, and a plurality of memory cells disposed between the first the second switch cells and connected to a plurality of word lines, and a control circuit configured to perform a program operation by providing a program voltage to a first word line among the plurality of word lines, a switch voltage to a second word line among the plurality of word lines, and a pass voltage to remaining word lines among the plurality of word lines, wherein the control circuit is configured to turn off the first switch cell and the second switch cell in a first section of the program operation, and configured to turn on the first switch cell and increase the switch voltage in a second section of the program operation later than the first section.

公开(公告)号：US20190019809A1

公开(公告)日：2019-01-17

申请号：US15941978

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Tae Hun KIM ,  Byoung Taek KIM ,  Jun Hee LIM

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575

Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.