公开(公告)号：US12073875B2

公开(公告)日：2024-08-27

申请号：US17943448

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Changsoo Yoon ,  Hyunyoon Cho ,  Junghwan Choi

IPC: G11C16/34 ,  G11C11/4096 ,  H03M1/12

CPC classification number: G11C11/4096 ,  H03M1/124 ,  G11C16/34

Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

公开(公告)号：US11972831B2

公开(公告)日：2024-04-30

申请号：US17827126

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Changsoo Yoon ,  Hyunyoon Cho ,  Junghwan Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/062 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14

Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

公开(公告)号：US20230120821A1

公开(公告)日：2023-04-20

申请号：US17827126

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSUB RIE ,  Eunseok Shin ,  Youngdon Choi ,  Changsoo Yoon ,  Hyunyoon Cho ,  Junghwan Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/14

Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.