公开(公告)号：US20180067847A1

公开(公告)日：2018-03-08

申请号：US15695060

申请日：2017-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOONNA OH ,  DEOK-GU YOON ,  SANGUHN CHA

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0207 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/12 ,  G11C8/12 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/1204 ,  G11C2029/4402

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.