公开(公告)号：US20210027835A1

公开(公告)日：2021-01-28

申请号：US16821265

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOJEON LEE ,  DUEUNG KIM ,  JIN-YOUNG KIM

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.