公开(公告)号：US20250062771A1

公开(公告)日：2025-02-20

申请号：US18804954

申请日：2024-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohun Jang ,  Junhyeok Yang ,  Hyuntaek Oh ,  Dokyung Lim ,  Chanyoung Jeong

IPC: H03L7/107 ,  H03L7/089 ,  H03L7/095

Abstract: There is provided a phase locked loop circuit including a phase-frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on first phase difference, and generate a first and a second control signals based on the phase gain, a lock detection circuit configured to generate a lock detection signal based on the first phase difference, a charge pump circuit configured to generate a loop filter input signal based on the first and second control signals, a loop filter configured to adjust impedance based on the activated lock detection signal and generate a loop filter output signal based on the adjusted impedance, an oscillator configured to generate a clock signal based on the loop filter output signal, and a divider configured to generate the feedback clock signal by dividing the clock signal.