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公开(公告)号：US12283884B2
公开(公告)日：2025-04-22
申请号：US17993603
申请日：2022-11-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungmin Yoo , Minsu Kim , Hyungmin Lee , Taehwang Kong , Junhyeok Yang , Woojoong Jung
Abstract: The present disclosure refers to direct current-to-direct current (DC-DC) converters and power supplies including the same. In an embodiment, a DC-DC converter includes a first switching circuit, a second switching circuit, a fourth capacitor coupled to a second node, and an inductor-capacitor (LC) filter coupled to a third node. The first switching circuit includes a first transistor coupled between a first capacitor and an input node, a second transistor coupled between the first capacitor and a second capacitor, a third transistor coupled between a first node and a third capacitor, and a fourth transistor coupled between the third capacitor and a ground node. The second switching circuit includes a fifth transistor coupled between the second capacitor and the third capacitor, a sixth transistor and a seventh transistor coupled between the first capacitor and the third capacitor, and an eighth transistor coupled between the first capacitor and the ground node.
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公开(公告)号：US11804778B2
公开(公告)日：2023-10-31
申请号：US17389806
申请日：2021-07-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmin Yoo , Taehwang Kong , Sangho Kim , Junhyeok Yang , Hyungmin Lee , Yunho Lee , Woojoong Jung
CPC classification number: H02M3/1588 , H02M1/08 , H02M3/157
Abstract: A direct-current (DC)-DC converter includes a converting circuit including an inductor element. The converting circuit is configured to generate an output voltage from an input voltage based on a switching operation. An inductor current emulator is configured to adjust at least one parameter for changing a current peak value of the inductor element in response to a change in a level of the input voltage and is configured to generate an internal voltage based on the at least one parameter, which is adjusted. The inductor current emulator is configured to generate a control signal for controlling the switching operation such that current of the inductor element has a pattern corresponding to a pattern of the internal voltage.
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公开(公告)号：US11340644B2
公开(公告)日：2022-05-24
申请号：US17315621
申请日：2021-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghoon Jung , Tae-Hwang Kong , Sangho Kim , Junhyeok Yang , Jeongpyo Park
Abstract: Disclosed is an electronic device, which includes an amplifier circuit that receives a feedback voltage and a reference voltage and amplifies a difference between the feedback voltage and the reference voltage to output an amplified difference voltage, an analog-to-digital converter that converts the amplified difference voltage to a digital code including two or more bits, and low-dropout (LDO) regulators that outputs output voltages based on the digital code. Each of the LDO regulators includes power transistors outputting a corresponding output voltage of the output voltages, drives one of the power transistors in a switching state, and drives each of remaining power transistors in a turned-on state or a turned-off state.
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公开(公告)号：US12212242B2
公开(公告)日：2025-01-28
申请号：US18468893
申请日：2023-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmin Yoo , Taehwang Kong , Sangho Kim , Junhyeok Yang , Hyungmin Lee , Yunho Lee , Woojoong Jung
Abstract: A direct-current (DC)-DC converter includes a converting circuit including an inductor element. The converting circuit is configured to generate an output voltage from an input voltage based on a switching operation. An inductor current emulator is configured to adjust at least one parameter for changing a current peak value of the inductor element in response to a change in a level of the input voltage and is configured to generate an internal voltage based on the at least one parameter, which is adjusted. The inductor current emulator is configured to generate a control signal for controlling the switching operation such that current of the inductor element has a pattern corresponding to a pattern of the internal voltage.
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5.发明授权公开(公告)号：US11797040B2
公开(公告)日：2023-10-24
申请号：US17385010
申请日：2021-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongpyo Park , Tae-Hwang Kong , Junhyeok Yang , Jooseong Kim
Abstract: An electronic device including: a reference voltage generator circuit to generate a reference voltage based on a first and second voltage, the reference voltage generator circuit including: a first current source to supply a first current to each of a first and second node; an amplifier to amplify a difference between the first voltage of the first node and the second voltage of the second node and to output a difference voltage corresponding to the amplified difference; a first bipolar junction transistor (BJT) connected to the first node; a first resistor connected to the second node; a second BJT connected between the first resistor and ground; a second resistor connected between the second node and ground; and a first transistor to be supplied with a second current from the first current source; and an adaptive cascode circuit to generate a bias voltage applied to a gate of the first transistor.
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Patent Agency Ranking
公开(公告)号：US20220222339A1
公开(公告)日：2022-07-14
申请号：US17470875
申请日：2021-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghun Heo , Kwangho Kim , Junhyeok Yang
Abstract: A low voltage attack detector includes: a low voltage detector configured to output a low voltage detection flag signal having a high level when a first power supply voltage reaches a first voltage level using a bandgap reference (BGR) circuit including a PMOS transistor and a first bipolar junction transistor (BJT) connected in series between the first power supply voltage and a second power supply voltage; a BGR operation region detector configured to output a malfunction detection flag signal having a high level when the first power supply voltage reaches a second voltage level lower than the first voltage level; and a logic gate configured to output a final low voltage detection flag signal having a high level when at least one of the low voltage detection flag signal and the malfunction detection flag signal has a high level.
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公开(公告)号：US12117472B2
公开(公告)日：2024-10-15
申请号：US17873795
申请日：2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeseung Lee , Sungmin Yoo , Taehwang Kong , Junhyeok Yang
IPC: G01R23/10
CPC classification number: G01R23/10
Abstract: An oscillation detector includes an amplitude variation detection circuit configured to generate a first pulse signal by comparing levels of voltages with each other, a frequency variation detection circuit configured to generate a second pulse signal by filtering the first pulse signal and allowing to pass a frequency component that is less than or equal to a certain frequency among frequency components of the first pulse signal, and a time variation detection circuit configured to output an oscillation detection signal when the second pulse signal has consecutive pulses for a period of time.
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公开(公告)号：US12079023B2
公开(公告)日：2024-09-03
申请号：US18374028
申请日：2023-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongpyo Park , Tae-Hwang Kong , Junhyeok Yang , Jooseong Kim
Abstract: An electronic device including: a reference voltage generator circuit to generate a reference voltage based on a first and second voltage, the reference voltage generator circuit including: a first current source to supply a first current to each of a first and second node; an amplifier to amplify a difference between the first voltage of the first node and the second voltage of the second node and to output a difference voltage corresponding to the amplified difference; a first bipolar junction transistor (BJT) connected to the first node; a first resistor connected to the second node; a second BJT connected between the first resistor and ground; a second resistor connected between the second node and ground; and a first transistor to be supplied with a second current from the first current source; and an adaptive cascode circuit to generate a bias voltage applied to a gate of the first transistor.
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公开(公告)号：US20250125724A1
公开(公告)日：2025-04-17
申请号：US18909152
申请日：2024-10-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doojin Jang , Hyunsik Kim , Junhyeok Yang , Sungmin Yoo , Honghyun Bae
Abstract: Provided is a hybrid buck converter including a first PMOS transistor and a second PMOS transistor electrically connecting a power supply voltage node with a first switching node, a first NMOS transistor and a second NMOS transistor electrically connecting a ground node with the first switching node, an inductor electrically connecting the first switching node with a second switching node, a third NMOS transistor electrically connecting the second switching node with a first output node, a third PMOS transistor electrically connecting the second switching node with a second output node, a shunt regulator that is driven based on a second output voltage of the second output node, a first PWM controller adjusting, based on a pulse width control of first PMOS transistor and first NMOS transistor, a magnitude of an inductor current, and a second PWM controller adjusting, based on a pulse width control of first PMOS transistor and first NMOS transistor, a magnitude of the second output voltage.
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公开(公告)号：US20250062771A1
公开(公告)日：2025-02-20
申请号：US18804954
申请日：2024-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dohun Jang , Junhyeok Yang , Hyuntaek Oh , Dokyung Lim , Chanyoung Jeong
Abstract: There is provided a phase locked loop circuit including a phase-frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on first phase difference, and generate a first and a second control signals based on the phase gain, a lock detection circuit configured to generate a lock detection signal based on the first phase difference, a charge pump circuit configured to generate a loop filter input signal based on the first and second control signals, a loop filter configured to adjust impedance based on the activated lock detection signal and generate a loop filter output signal based on the adjusted impedance, an oscillator configured to generate a clock signal based on the loop filter output signal, and a divider configured to generate the feedback clock signal by dividing the clock signal.
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