公开(公告)号：US20160041578A1

公开(公告)日：2016-02-11

申请号：US14635145

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hee LEE ,  Bong-Kyu KIM ,  Dong-Chul CHOI ,  Gun-Il KANG

IPC: G06F1/10 ,  G06F1/12 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  G06F13/4022

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

Abstract translation: 时钟切换装置包括控制器和开关电路。 当模式信号的逻辑电平改变时，控制器使用控制信号设置时钟切换周期。 开关电路接收第一时钟信号，第二时钟信号和辅助时钟信号。 开关电路基于控制信号，在时钟切换期间之前，将第一时钟信号和第二时钟信号之间的一个时钟信号作为无毛刺时钟信号输出，停止输出一个时钟信号，并输出辅助时钟信号 在时钟切换期间内无毛刺时钟信号，停止输出辅助时钟信号，并在第一时钟信号和第二时钟信号之间输出另一个时钟信号作为时钟切换周期后的无毛刺时钟信号。