公开(公告)号：US20190311954A1

公开(公告)日：2019-10-10

申请号：US16450383

申请日：2019-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  Jin Tae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

IPC: H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  G06F17/50

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US20170287787A1

公开(公告)日：2017-10-05

申请号：US15624039

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  JinTae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

IPC: H01L21/8234 ,  G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.