公开(公告)号：US20210313001A1

公开(公告)日：2021-10-07

申请号：US17073682

申请日：2020-10-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungik JANG ,  Kihyun KIM ,  Soojin ANN ,  Chungki Lee ,  Dongguk HAN

IPC分类号： G11C29/38 ,  G11C29/44 ,  G11C11/4091 ,  H01L25/065

摘要： A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.