公开(公告)号：US11423970B2

公开(公告)日：2022-08-23

申请号：US17319253

申请日：2021-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongheon Yu ,  Joungyeal Kim ,  Doowon Bong

IPC: G11C11/40 ,  G06F1/12 ,  G11C11/4076 ,  G11C11/4072

Abstract: A memory device includes a command decoder configured to receive a command, a data clock receiving circuit configured to receive a data clock signal, and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit. The control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command. The data clock receiving circuit is in an enabled state until a predetermined particular command is received.

公开(公告)号：US11031068B2

公开(公告)日：2021-06-08

申请号：US16834090

申请日：2020-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongheon Yu ,  Joungyeal Kim ,  Doowon Bong

IPC: G11C11/40 ,  G11C11/4076 ,  G06F1/12 ,  G11C11/4072

Abstract: A memory device includes a command decoder configured to receive a command, a data clock receiving circuit configured to receive a data clock signal, and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit. The control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command. The data clock receiving circuit is in an enabled state until a predetermined particular command is received.