公开(公告)号：US20220013370A1

公开(公告)日：2022-01-13

申请号：US17197274

申请日：2021-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEON HO LEE ,  YEONSEOK KIM ,  Eunyeong KIM

IPC: H01L21/48 ,  H01L25/00 ,  H01L21/683

Abstract: Disclosed is a method of fabricating a semiconductor package. The method may include providing a preliminary interposer substrate including connection terminals on a carrier substrate such that the connection terminals are oriented outward, preparing a release film including a base layer, an intermediate layer, and an adhesive layer, attaching the connection terminals to a first surface of the release film, detaching the carrier substrate from the preliminary interposer substrate, cutting the preliminary interposer substrate to form a plurality of interposer substrates separated from each other, irradiating a first light of a first wavelength onto the release film to form an air gap between the connection terminals and the release film, and detaching the interposer substrates from the release film. The intermediate substrate may include a light absorber absorbing the first light.

公开(公告)号：US20220367401A1

公开(公告)日：2022-11-17

申请号：US17540519

申请日：2021-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunyeong KIM ,  Yeongseok KIM ,  Jihwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.