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公开(公告)号：US20150093857A1
公开(公告)日：2015-04-02
申请号：US14566685
申请日：2014-12-10
发明人： Jihwan HWANG , Young Kun JEE , Jung-Hwan KIM , Tae Hong MIN , Kwang-chul CHOI
CPC分类号： H01L25/50 , H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/3185 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06582 , H01L2924/1431 , H01L2924/1434 , H01L2924/00
摘要： Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.
摘要翻译： 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。
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公开(公告)号：US20210375823A1
公开(公告)日：2021-12-02
申请号：US17142133
申请日：2021-01-05
发明人： Jihwan HWANG , Unbyoung KANG , Sangsick PARK , Jihwan SUH , Soyoun LEE , Teakhoon LEE
IPC分类号： H01L23/00 , H01L23/498 , H01L25/065
摘要： A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
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公开(公告)号：US20220285312A1
公开(公告)日：2022-09-08
申请号：US17804110
申请日：2022-05-26
发明人： Jihwan HWANG , Unbyoung KANG , Sangsick PARK , Jihwan SUH , Soyoun LEE , Teakhoon LEE
IPC分类号： H01L23/00 , H01L25/065 , H01L23/498
摘要： A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
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公开(公告)号：US20220130801A1
公开(公告)日：2022-04-28
申请号：US17568558
申请日：2022-01-04
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538 , H01L23/31 , H01L23/16
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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公开(公告)号：US20220367401A1
公开(公告)日：2022-11-17
申请号：US17540519
申请日：2021-12-02
发明人： Eunyeong KIM , Yeongseok KIM , Jihwan HWANG
IPC分类号： H01L23/00 , H01L25/065 , H01L25/10 , H01L23/498
摘要： A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.
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公开(公告)号：US20220344308A1
公开(公告)日：2022-10-27
申请号：US17861580
申请日：2022-07-11
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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7.发明公开公开(公告)号：US20240071942A1
公开(公告)日：2024-02-29
申请号：US18120826
申请日：2023-03-13
发明人： Young kun JEE , Jihwan HWANG , Chungsun LEE
IPC分类号： H01L23/538 , H01L23/00
CPC分类号： H01L23/5386 , H01L23/5384 , H01L24/06 , H01L2224/06051 , H01L2224/06102 , H01L2224/08146
摘要： A semiconductor chip including a semiconductor substrate having first and second surfaces, a transistor on the first surface, a first interlayer dielectric layer on the transistor, a second interlayer dielectric layer on the first interlayer dielectric layer, a wiring line in the second interlayer dielectric layer, a first conductive pad on the second interlayer dielectric layer, a first passivation layer on the second interlayer dielectric layer, a second conductive pad in the first passivation layer, a through via penetrating the semiconductor substrate and the first interlayer dielectric layer to come into connection with the wiring line, a second passivation layer on the second surface, and a third conductive pad in the second passivation layer and connected to the through via. The first passivation layer has a first thickness 0.4 to 0.6 times a second thickness between the first surface and a top surface of the second passivation layer.
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公开(公告)号：US20210151410A1
公开(公告)日：2021-05-20
申请号：US17036508
申请日：2020-09-29
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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公开(公告)号：US20210028152A1
公开(公告)日：2021-01-28
申请号：US16833761
申请日：2020-03-30
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/538
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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