公开(公告)号：US20210305150A1

公开(公告)日：2021-09-30

申请号：US17032100

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGMIN KIM ,  BEYOUNGHYUN KOH ,  YONGJIN KWON ,  JOONGSHIK SHIN ,  GUNWOOK YOON

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00

Abstract: A memory device including a substrate; a lower conductive layer on the substrate; a stacked structure including gate layers and interlayer insulating layers alternately stacked on the lower conductive layer; a channel structure in a channel hole that penetrates the stacked structure in a vertical direction; and a common source line structure in a common source line trench that penetrates the lower conductive layer and the stacked structure in the vertical direction. The common source line structure includes a side insulating layer on a side surface of the common source line trench, a central insulating layer at a central portion of the common source line trench, an intermediate conductive layer between the side insulating layer and the central insulating layer, and an upper conductive layer at an upper portion of the common source line trench.