公开(公告)号：US20210134831A1

公开(公告)日：2021-05-06

申请号：US16902489

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20170207234A1

公开(公告)日：2017-07-20

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNMOG PARK ,  DAEWOONG KANG ,  CHADONG YEO ,  JAEHOON JANG ,  JOONGSHIK SHIN

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/11529 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/16 ,  H01L29/4966

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

公开(公告)号：US20210305150A1

公开(公告)日：2021-09-30

申请号：US17032100

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGMIN KIM ,  BEYOUNGHYUN KOH ,  YONGJIN KWON ,  JOONGSHIK SHIN ,  GUNWOOK YOON

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00

Abstract: A memory device including a substrate; a lower conductive layer on the substrate; a stacked structure including gate layers and interlayer insulating layers alternately stacked on the lower conductive layer; a channel structure in a channel hole that penetrates the stacked structure in a vertical direction; and a common source line structure in a common source line trench that penetrates the lower conductive layer and the stacked structure in the vertical direction. The common source line structure includes a side insulating layer on a side surface of the common source line trench, a central insulating layer at a central portion of the common source line trench, an intermediate conductive layer between the side insulating layer and the central insulating layer, and an upper conductive layer at an upper portion of the common source line trench.

公开(公告)号：US20220310651A1

公开(公告)日：2022-09-29

申请号：US17806842

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20220077167A1

公开(公告)日：2022-03-10

申请号：US17343330

申请日：2021-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GEUNWON LIM ,  MINJUN KANG ,  BYUNGGON PARK ,  JOONGSHIK SHIN

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  G11C7/18 ,  H01L23/528

Abstract: A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.