公开(公告)号：US20190148403A1

公开(公告)日：2019-05-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  HYEONG PARK ,  HYUNMIN LEE ,  HOJONG KANG ,  JOOWON PARK ,  SEUNGMIN SONG

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.