公开(公告)号：US20190148403A1

公开(公告)日：2019-05-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  HYEONG PARK ,  HYUNMIN LEE ,  HOJONG KANG ,  JOOWON PARK ,  SEUNGMIN SONG

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US20190333923A1

公开(公告)日：2019-10-31

申请号：US16235217

申请日：2018-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  MINYEONG SONG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.

公开(公告)号：US20210074724A1

公开(公告)日：2021-03-11

申请号：US17073786

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  Young-Jin Jung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11526 ,  H01L27/11575 ,  H01L27/11548

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

公开(公告)号：US20200212061A1

公开(公告)日：2020-07-02

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGYOON CHOI ,  DONG-SIK LEE ,  JONGWON KIM ,  GILSUNG LEE ,  EUNGSUK CHO ,  BYUNGYONG CHOI ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.