公开(公告)号：US09928799B2

公开(公告)日：2018-03-27

申请号：US14851265

申请日：2015-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HaJun Lee ,  Jin-Han Kim ,  Junho Song ,  SeongJong Yoo ,  Yeonwoo Jung ,  Yong-Hun Kim ,  Keemoon Chun

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08

Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.