SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

    公开(公告)号:US20250105152A1

    公开(公告)日:2025-03-27

    申请号:US18823789

    申请日:2024-09-04

    Inventor: Hansae Lim

    Abstract: A semiconductor package includes a package substrate including wirings having a plurality of pad patterns that respectively extend such that at least a portion of each of the pad patterns is exposed in at least one pad open region, a semiconductor chip mounted on the chip mounting region of the package substrate by a plurality of conductive bumps, and a sealing member on the semiconductor chip on the package substrate. Each of the plurality of pad patterns includes a main line extending in a first direction away from one side of the pad open region, and a branch line extending in a second direction different from the first direction from an end portion of the main line or from a position laterally spaced apart from the end portion of the main line.

    SEMICONDUCTOR PACKAGES INCLUDING DAM STRUCTURES

    公开(公告)号:US20250062167A1

    公开(公告)日:2025-02-20

    申请号:US18731445

    申请日:2024-06-03

    Inventor: Hansae Lim

    Abstract: A semiconductor package includes a substrate including lower pads and a vent hole, a semiconductor chip, an encapsulant including a through-portion filling the vent hole and an extension disposed adjacent to the through-portion, and a ground plate and a power plate disposed on a lower surface of the substrate. The lower surface of the substrate includes a first region including the vent hole, a pad region including the lower pads, and a second region between the first region and the pad region. The extension extends in a first horizontal direction in the first region. The ground plate and the power plate include at least one first protrusion disposed in the second region and extending in the first horizontal direction and at least one second protrusion extending in an opposite direction, respectively. The at least one first protrusion is disposed to engage with the at least one second protrusion.

    SEMICONDUCTOR PACKAGE AND WIRING SUBSTRATE USED FOR THE SAME

    公开(公告)号:US20250125245A1

    公开(公告)日:2025-04-17

    申请号:US18628890

    申请日:2024-04-08

    Inventor: Hansae Lim

    Abstract: A semiconductor package includes a wiring substrate including a wiring pattern, a solder resist layer disposed on the wiring pattern and including an opening region, and a first penetrating contact disposed in the opening region of the solder resist layer. The semiconductor chip disposed in the opening region and connected to the wiring substrate. The molding portion includes a first portion covering the semiconductor chip and a second portion disposed below the semiconductor chip. The second portion includes a penetrating molding portion disposed in the first penetrating contact.

    SEMICONDUCTOR CHIPS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

    公开(公告)号:US20250046768A1

    公开(公告)日:2025-02-06

    申请号:US18440991

    申请日:2024-02-14

    Inventor: Hansae Lim

    Abstract: A semiconductor chip according to some embodiments may include a main area, and an edge area that is positioned on a side of the main area in a first direction. On the main area, main area chip pads may be provided, and on the edge area, edge area chip pads may be provided. The edge area chip pads may be arranged such that two edge area chip pads immediately adjacent to each other in the first direction may be spaced apart from each other in a direction intersecting the first direction.

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