公开(公告)号：US20230091567A1

公开(公告)日：2023-03-23

申请号：US18073079

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun JIN ,  Yongjae LEE ,  Seunghan KIM ,  Hyoungjoo KIM

IPC: G06F3/06 ,  G11C29/56 ,  G11C29/10

Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.

公开(公告)号：US20220188027A1

公开(公告)日：2022-06-16

申请号：US17375168

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun JIN ,  Yongjae LEE ,  Seunghan KIM ,  Hyoungjoo KIM

IPC: G06F3/06

Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.