公开(公告)号：US10157259B2

公开(公告)日：2018-12-18

申请号：US15407365

申请日：2017-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Min Jo ,  Yoo Hwan Kim ,  Hye Won Shim ,  Sang Woo Pae

IPC: G06F17/50 ,  G01R31/28

Abstract: A method for predicting a failure rate of a semiconductor integrated circuit includes receiving a circuit netlist corresponding to circuit defining data, which defines a connection relation, input, output, size, type and operating temperature of each transistor of a plurality of transistors included in the semiconductor integrated circuit. Low-risk transistors having a low-failure probability among the plurality of transistors are detected and filtered out based on the circuit netlist. Failure rates are calculated of respective high-risk transistors other than the low-risk transistors among the plurality of transistors. A total failure rate of the semiconductor integrated circuit is calculated based on the failure rates of the respective high-risk transistors.