公开(公告)号：US20240147739A1

公开(公告)日：2024-05-02

申请号：US18208979

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hong KIM ,  Tae-Seok JANG ,  Hyun-Mook CHOI

IPC: H10B63/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B63/845 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B63/34 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: A semiconductor memory device comprising a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes a cell substrate including a first face facing the peripheral circuit structure and a second face opposite the first face, a first mold stack including a plurality of first gate electrodes sequentially stacked on the first face, and a channel hole extending through the plurality of first gate electrodes. A channel structure includes a gate dielectric film, a semiconductor film, and a variable resistance film sequentially stacked in the channel hole, wherein the semiconductor film includes a sidewall portion intersecting the first face and the plurality of first gate electrodes, and a top plate portion extending from the sidewall portion in the cell substrate in a parallel manner to the first face.