公开(公告)号：US20230200077A1

公开(公告)日：2023-06-22

申请号：US18080013

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjung LEE ,  Jaeho CHOI ,  Hanmei CHOI

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes: a periphery circuit structure on a substrate; and a memory cell array on the periphery circuit structure, and including memory cells arranged in a first direction substantially perpendicular to an upper surface of the substrate, wherein the periphery circuit structure includes: a first element separation layer on the substrate and defining a first active region; a channel semiconductor layer on the first active region and at a higher level than an upper surface of the first element separation layer; a first gate structure on the channel semiconductor layer; a second element separation layer on the substrate, defining a second active region and a third active region, and including an upper surface at a higher level than the upper surface of the first element separation layer; a second gate structure on the second active region; and a third gate structure on the third active region.

公开(公告)号：US20250024667A1

公开(公告)日：2025-01-16

申请号：US18771723

申请日：2024-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo KANG ,  Hyunjung LEE ,  Jaehong PARK

IPC: H10B12/00

Abstract: Provided is a semiconductor device including a peripheral circuit structure including peripheral circuit transistors, bit lines on the peripheral circuit structure and extending in a first horizontal direction, back gate lines extending in a second horizontal direction at a vertical level higher than the bit lines, word lines extending in the second horizontal direction at a vertical level higher than the bit lines and alternating with the back gate lines, a plurality of vertical channel layers in a matrix form on the bit lines, each of the vertical channel layers including a first sidewall extending in a vertical direction and facing a corresponding back gate line, a second sidewall opposite to the first sidewall and facing a corresponding word line, a part of the second sidewall adjacent to a bit line having a curved shape, contact pads on the vertical channel layers, and storage nodes on the contact pads.