公开(公告)号：US20170244030A1

公开(公告)日：2017-08-24

申请号：US15362906

申请日：2016-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-mok PARK ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

公开(公告)号：US20190013466A1

公开(公告)日：2019-01-10

申请号：US16109914

申请日：2018-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-mok PARK ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.