公开(公告)号：US20240074336A1

公开(公告)日：2024-02-29

申请号：US17894549

申请日：2022-08-24

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Timothy Mathew Philip ,  Jin Ping Han ,  Ching-Tzu Chen ,  Kevin W. Brew ,  Lili Cheng

IPC: H01L45/00

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A memory device and method of forming a projection liner under a mushroom phase change memory device with sidewall electrode process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.

公开(公告)号：US20240016072A1

公开(公告)日：2024-01-11

申请号：US17859013

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hengyuan Lee ,  Yu-Sheng Chen ,  Cheng-Chun Chang ,  Xinyu BAO

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/126 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.

公开(公告)号：US20230320105A1

公开(公告)日：2023-10-05

申请号：US17693340

申请日：2022-03-12

Applicant: International Business Machines Corporation

Inventor： Guy M. Cohen ,  Takashi Ando ,  Nanbo Gong

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: A solid-state switch structure including a first solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following a first type programming pulse and a low electrical resistance obtained following a second type programming pulse, a second solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following said second type programming pulse and a low electrical resistance obtained following said first type programming pulse, a first contact made to a first end of said first solid-state material, a second contact made to a first end of said second solid-state material, a third contact made to a second end of said first solid-state material and to a second end of said second solid-state material.

公开(公告)号：US20230284464A1

公开(公告)日：2023-09-07

申请号：US17939859

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/249 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/228 ,  H01L27/2454 ,  H01L43/02 ,  H01L45/126 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

公开(公告)号：US20230189667A1

公开(公告)日：2023-06-15

申请号：US17547152

申请日：2021-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Ching-Tzu Chen ,  Carl Radens

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

公开(公告)号：US20230170022A1

公开(公告)日：2023-06-01

申请号：US17993118

申请日：2022-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Elisa PETRONI ,  Andrea REDAELLI

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0069 ,  H01L45/126 ,  H01L45/144 ,  H01L45/06

Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.

公开(公告)号：US11653579B2

公开(公告)日：2023-05-16

申请号：US17166474

申请日：2021-02-03

Applicant: STMicroelectronics S.r.l. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Paolo Giuseppe Cappelletti ,  Gabriele Navarro

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/0069 ,  H01L45/126 ,  H01L45/144 ,  G11C2013/008

Abstract: Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.

公开(公告)号：US20190148456A1

公开(公告)日：2019-05-16

申请号：US16226855

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhe Wu ,  Dong-ho Ahn ,  Hideki Horii ,  Soon-oh Park ,  Jeong-hee Park ,  Jin-woo Lee ,  Dong-jun Seong ,  Seol Choi

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

公开(公告)号：US20190097129A1

公开(公告)日：2019-03-28

申请号：US16185161

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20190051826A1

公开(公告)日：2019-02-14

申请号：US16164510

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Thomas R. Omstead ,  Cole S. Franklin

IPC: H01L45/00 ,  C23C16/36 ,  C23C16/455 ,  H01L21/02 ,  C23C16/34 ,  H01L27/24 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L45/124 ,  C23C16/345 ,  C23C16/36 ,  C23C16/45534 ,  C23C16/45542 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/283 ,  H01L21/76829 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16

Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.