公开(公告)号：US11855658B1

公开(公告)日：2023-12-26

申请号：US17882306

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Amit Berman ,  Avner Dor ,  Yaron Shany ,  Ilya Shapir ,  Ariel Doubchak

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11

CPC classification number: H03M13/1515 ,  H03M13/1108 ,  H03M13/1545 ,  H03M13/1575

Abstract: A processing circuit is configured to: construct a first locator polynomial for a Reed-Solomon codeword to identify locations of erasures in the Reed-Solomon codeword; determine a first syndrome of the Reed-Solomon codeword; calculate a first error evaluator polynomial from the first syndrome and the first locator polynomial; and perform error detection based on the first error evaluator polynomial to determine presence of errors in the Reed-Solomon codeword. When presence of errors in the Reed-Solomon codeword is not detected in the error detection, the processing circuit bypasses updating the first locator polynomial and proceeds to completing decoding of the Reed-Solomon codeword, but when presence of errors in the Reed-Solomon codeword is detected in the error detection, the system first updates the first locator polynomial to a second locator polynomial in a process with reduced complexity compared to the common one, before completing decoding of the Reed-Solomon codeword.