公开(公告)号：US20190066773A1

公开(公告)日：2019-02-28

申请号：US15915660

申请日：2018-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hyun Park ,  In-Hak Lee ,  Jae-Seung Choi

IPC: G11C11/419 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/14 ,  H01L27/11

Abstract: A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

公开(公告)号：US10319433B2

公开(公告)日：2019-06-11

申请号：US15915660

申请日：2018-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hyun Park ,  In-Hak Lee ,  Jae-Seung Choi

IPC: G11C11/419 ,  G11C7/18 ,  G11C11/408 ,  H01L27/11 ,  G11C7/14 ,  G11C11/4097

Abstract: A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.