公开(公告)号：US09864687B2

公开(公告)日：2018-01-09

申请号：US15198583

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sik Kim ,  Woo Hyung Chun ,  Seong Min Jo ,  Jae Young Hur

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0831 ,  G06F12/1433 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/621

Abstract: An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

公开(公告)号：US09390007B2

公开(公告)日：2016-07-12

申请号：US14452586

申请日：2014-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Young Hur ,  Sang woo Rhim ,  Beom Hak Lee

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0292 ,  G06F12/0607

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract translation: 显示系统包括：映射存储器，包括被配置为存储对应于图像的多个图像块的多个存储器组;以及图像映射部件，被配置为根据所述多个存储器组中的每一个将所述多个存储体中的每一个分配给所述多个存储体中的一个 第一映射或第二映射，其中所述图像映射组件基于所述第一和第二映射的存储体交织度量来确定是否使用所述第一或第二映射。

公开(公告)号：US20140218378A1

公开(公告)日：2014-08-07

申请号：US14169410

申请日：2014-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG HO ROH ,  Kyoung Man Kim ,  Young Mok Song ,  Jong Hyup Lee ,  Jae Young Hur ,  Sung Min Hong ,  Byung Tak Lee ,  Kee Moon Chun

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G5/393 ,  G09G2330/021

Abstract: A system on chip (SoC) and a method of operating the same are provided. The SoC includes a central processing unit (CPU) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the CPU; a UD unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the CPU; a memory controller storing the update region in the memory according to the control of the CPU; and a display controller accessing the memory and outputting the update region to a display device according to the control of the CPU.

Abstract translation: 提供了片上系统（SoC）及其操作方法。 SoC包括：基于图像生成和中断信号控制图像的当前帧的存储器操作和显示操作的中央处理单元（CPU）; 图像生成器，根据CPU的控制从存储器请求当前帧的数据; 确定当前帧是否被更新的UD单元，基于包括在图像生成器的请求中的虚拟地址来检测更新区域是否是部分帧，并将与更新区域相对应的中断信号输出到CPU; 存储器控制器，其根据CPU的控制将更新区域存储在存储器中; 以及显示控制器，其访问存储器并根据CPU的控制将更新区域输出到显示设备。

公开(公告)号：US10692171B2

公开(公告)日：2020-06-23

申请号：US15353226

申请日：2016-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Hong ,  Jae Young Hur ,  Min Je Jun

IPC: G06T1/60 ,  G06F12/06 ,  G06T3/60 ,  H04N5/76

Abstract: A method of generating a virtual address in a data processing system controller includes receiving and analyzing attribute information which indicates whether user intervention is possible for allocating a memory buffer for storing image data; enabling one of a first virtual address generator or a second virtual address generator based on an analysis result; and generating the virtual address of a data transaction using the enabled virtual address generator.

公开(公告)号：US10198357B2

公开(公告)日：2019-02-05

申请号：US15240212

申请日：2016-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Young Hur ,  Sung Min Hong

IPC: G06F12/0831

Abstract: A coherent interconnect is provided. The coherent interconnect includes a snoop filter and a circuit that receives a write request, strobe bits, and write data from a central processing unit (CPU); generates a snoop filter request based on the write request; and transmits, at substantially the same time, the snoop filter request to the snoop filter and the write request, the strobe bits, and the write data to a memory controller.