公开(公告)号：US20240081062A1

公开(公告)日：2024-03-07

申请号：US18143915

申请日：2023-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon KIM ,  Jiyoung KIM ,  In ho KANG ,  Woosung YANG ,  Jae-Eun LEE

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory includes a substrate that includes pass transistor regions, a peripheral circuit structure that includes pass transistors on the pass transistor regions, and a cell array structure on the peripheral circuit structure, the cell array structure including a plurality of cell array regions and a plurality of connection regions that are alternately arranged along a first direction. The cell array structure includes a stack structure including conductive patterns vertically stacked and correspondingly connected to the pass transistors. The stack structure includes stepwise structures on the connection regions. The connection regions of the cell array structure correspondingly overlap the pass transistor regions of the peripheral circuit structure.